Abstract: A device structure includes semiconductor devices located on a substrate; metal interconnect structures located in dielectric material layers overlying the semiconductor devices; and a non-Ohmic voltage-triggered switch including a first switch electrode that is electrically connected to one of the semiconductor devices through a subset of the metal interconnect structures, a second switch electrode, and a non-Ohmic switching material portion providing a non-Ohmic current-voltage characteristics and in contact with the first switch electrode and the second switch electrode. The non-Ohmic voltage-triggered switch may be used as an electrostatic discharge (ESD) switch.

Abstract: An embodiment phase change material (PCM) switch may include a phase change material element, a first electrode, a second electrode, and a direct heating element including an ionic resistance change material contacting the phase change material element. The phase change material element may include a phase change material that switches from an electrically conducting phase to an electrically insulating phase or from an electrically insulating phase to an electrically conducting phase by application of a heat pulse generated by the heating element. The PCM switch may further include a switching electrode contacting the ionic resistance change material such that the ionic resistance change material may be switched from a high resistance to a low resistance state by application of voltages to the first electrode, the second electrode, and the switching electrode. Electrical currents within the ionic resistance change material may generate heat that switches the phase change material element.

Abstract: A device structure includes a parallel connection of capacitor-switch assemblies located over a substrate. The capacitor-switch assemblies include a first capacitor-switch assembly that includes a first series connection of a first capacitor and a first non-Ohmic switching device, which has a first threshold voltage and includes a first primary switch electrode, a first secondary switch electrode, and a first non-Ohmic switching material portion. The capacitor switch assemblies further include a second capacitor-switch assembly that includes a second series connection of a second capacitor and a second non-Ohmic switching device, which has a second threshold voltage and includes a second primary switch electrode, a second secondary switch electrode, and a second non-Ohmic switching material portion. The second threshold voltage is different from the first threshold voltage. The non-Ohmic switching devices may be conditionally turned on depending on a magnitude of applied voltage spikes.

Abstract: A semiconductor structure according to the present disclosure includes a conductive feature in a top portion of a substrate, a bottom electrode layer over and in electrical coupling with the conductive feature, an insulator layer over the bottom electrode layer, a semiconductor layer over the insulator layer, a ferroelectric layer over the semiconductor layer, and a top electrode layer over the ferroelectric layer. The semiconductor layer includes a plurality of portions with different thicknesses.

Abstract: A semiconductor may include a handle substrate, a semiconductor material layer on which semiconductor devices, metal interconnect structures, dielectric material layers, and an inductor structure are located, and a patterned magnetic shielding layer including at least one portion of a ferromagnetic material having relative permeability of at least 20 and disposed between the semiconductor material layer and the handle substrate and reducing electromagnetic coupling between the inductor structure and the handle substrate.

Abstract: A device structure includes a voltage regulator circuit, which includes: a first semiconductor die including a pulse width modulation (PWM) circuit and connected to a PWM voltage output node at which a pulsed voltage output is generated; and a series connection of an inductor and a parallel connection circuit, the parallel connection circuit including a parallel connection of capacitor-switch assemblies. A first end node of the series connection is connected to the PWM voltage output node; a second end node of the series connection is connected to electrical ground; each of the capacitor-switch assemblies includes a respective series connection of a respective capacitor and a respective switch; and each switch within the capacitor-switch assemblies is located within the first semiconductor die.

Abstract: A display method for an electronic label having a display area is disclosed. The display method includes the following steps. A plurality of visual contents to be displayed are predefined, wherein each of the visual contents has a first state and a second state corresponding to a first state display subpage and a second state display page respectively. The display area is divided into a plurality of first sub-areas for displaying the plurality of first state display subpages respectively. A second sub-area operable for selection of a specific one from the plurality of first state display subpages is provided in each of the first sub-area in response to a first instruction of a user. The display area is caused to display the second state display page corresponding to the specific first state display subpage in response to a second instruction of the user.

Abstract: The present disclosure relates to an integrated chip including a first metal layer over a substrate. A second metal layer is over the first metal layer. An ionic crystal layer is between the first metal layer and the second metal layer. A metal oxide layer is between the first metal layer and the second metal layer. The first metal layer, the second metal layer, the ionic crystal layer, and the metal oxide layer are over a transistor device that is arranged along the substrate.

Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device comprising a chimney seed structure. A ferroelectric layer overlies a bottom electrode layer, and a top electrode layer overlies the ferroelectric layer. The top electrode layer, the ferroelectric layer, and the bottom electrode layer form a plurality of memory cells, and a dielectric wall extends through the top electrode layer and segments the top electrode layer into a plurality top electrodes individual to the memory cells. The chimney seed structure underlies the ferroelectric layer and extends through the bottom electrode layer from the ferroelectric layer. The chimney seed structure is configured to seed ferroelectric crystalline growth in the ferroelectric layer to allow the ferroelectric layer to achieve a large remanent polarization with a small thickness. The small thickness increases read speeds, while the large remanent polarization increases a read window and hence reliability.

Abstract: A resistive random access memory (ReRAM) apparatus is provided. The ReRAM apparatus includes a plurality of memory cells, each of the memory cells comprises a transistor and a resistor; a bit line connected to a first terminal of the resistor of each of the memory cells; a local source line connected to a source electrode of the transistor of each of the memory cells; and a driving cell connected between the local source line and a global source line. A method for operating the ReRAM apparatus is also provided.

Abstract: A semiconductor structure may be located over a substrate, and may include a parallel connection of a first component and a second component. The first component includes a series connection of a diode and a capacitor that is selected from a metal-ferroelectric-metal capacitor and a metal-antiferroelectric-metal capacitor. The second component includes a battery structure. The semiconductor structure may be used as a combination of an energy harvesting device and an energy storage structure that utilizes heat from adjacent semiconductor devices or from other heat sources.

Abstract: A semiconductor structure may include semiconductor devices located on a substrate, metal interconnect structures that are located within dielectric material layers overlying the semiconductor devices and are electrically connected to the semiconductor devices, and an energy harvesting device located over the metal interconnect structures and comprising a Schottky barrier diode, a first diode electrode located on a first side of the Schottky barrier diode, and a second diode electrode connected to a second side of the Schottky barrier diode

Abstract: Device structures and methods for forming the same are provided. A semiconductor structure according to the present disclosure includes a first electrode and a second electrode disposed over a substrate, a heating element disposed over the substrate, a phase-change material layer disposed over the substrate, and an insulator disposed vertically between the heating element and the phase-change material layer. The phase-change material layer includes at least a first segment and a second segment separated from the first segment. Each of the first and second segments overlaps the heating element in a top view. Each of the first and second segments is electrically connected with both the first and second electrodes.

Abstract: A composite material structure, including an outer layer, an inner layer, and a middle layer, is provided. The outer layer includes a metallic material. The inner layer includes a fiber material and a resin material. The outer layer has a first thickness, the inner layer has a second thickness, and the first thickness is different from the second thickness. The middle layer includes an adhesive material and is disposed between the outer layer and the inner layer. Two opposite surfaces of the middle layer are respectively in direct contact with the outer layer and the inner layer. A manufacturing method of the composite material structure is also provided.

Abstract: A semiconductor device includes a first film, a second film, and a third film that each include a phase change material (PCM) and are arranged with respect to one another along a first lateral direction. The semiconductor device includes a first metal pad, a second metal pad, a third metal pad, and a fourth metal pad. The first and second metal pads are disposed over ends of the first film, respectively, the second and third metal pads are disposed over ends of the second film, respectively, and the third and fourth metal pads are disposed over ends of the third film, respectively. The semiconductor device includes a first heater, a second heater, and a third heater, respectively disposed below the first film, the second film, and the third film.

Abstract: Some implementations described herein provide an inductor device formed in a substrate of a semiconductor device including an integrated circuit device. The inductor device may use one or more conduction layers that are included in the substrate. Furthermore, the inductor device may be electrically coupled to the integrated circuit device. By forming the inductor device in the substrate of the semiconductor device, an electrical circuit including the inductor device and the integrated circuit device may be formed within a single semiconductor device.

Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip comprising a ferroelectric structure disposed between a first conductive interconnect structure and a second conductive interconnect structure. The first conductive interconnect structure overlies a substrate. The second conductive interconnect structure overlies the first conductive interconnect structure. The second conductive interconnect structure comprises a conductive wire segment directly overlying a conductive via segment.

Abstract: Phase change material (PCM) switches and methods of fabrication thereof that include a phase change material layer and a selector having a first electrode and an ovonic threshold switching (OTS) material layer. The first electrode may selectively apply a bias voltage to the OTS layer, causing localized heating within the OTS layer. The phase change material layer may be in thermal contact with the OTS layer such that the OTS layer may heat an active region of the phase change material layer. By controlling the voltage applied to the first electrode and the resultant heating within the OTS layer, the active region of the phase change material layer may be selectively transitioned between a high resistivity state and a low resistivity state. A PCM switch according to various embodiments may enable low power and fast switching between high resistivity and low resistivity states and reduced parasitic capacitance.

Abstract: A semiconductor structure may include semiconductor devices located on a substrate, metal interconnect structures that are located within dielectric material layers overlying the semiconductor devices and are electrically connected to the semiconductor devices, and an energy harvesting device located over the metal interconnect structures and comprising a Schottky barrier diode, a first diode electrode located on a first side of the Schottky barrier diode, and a second diode electrode connected to a second side of the Schottky barrier diode.