Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: An interfacial layer is formed in a manner that enables a ferroelectric layer to be formed such that formation of ferroelectric crystalline phases (e.g., orthorhombic crystalline phases) in the ferroelectric layer is increased and formation of non-ferroelectric crystalline phases (e.g., monoclinic phases, tetragonal phases) in the ferroelectric layer is reduced. To achieve this, the grain size and/or other properties of the interfacial layer may be controlled during formation of the interfacial layer such that the grain size and/or other properties of the interfacial layer facilitate formation of a larger grain size in the ferroelectric layer. At larger grain sizes in the ferroelectric layer, the concentration of the ferroelectric crystalline phases in the crystal structure of the ferroelectric layer may be increased relative to if the ferroelectric layer were formed to a smaller grain size.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: Devices and method for forming a switch including a heater layer including a first heater pad, a second heater pad, and a heater line connecting the first heater pad and the second heater pad, a phase change material (PCM) layer positioned in a same vertical plane as the heater line, and a floating spreader layer including a first portion positioned in the same vertical plane as the heater line and the PCM layer, in which the first portion has a first width that is less than or equal to a distance between proximate sidewalls of the first heater pad and the second heater pad.

Abstract: A switch includes a heater layer, a phase change material (PCM) layer on the heater layer, and a spreader layer formed in proximity to the PCM layer and including a central region with a first thermal conductivity and an edge region with a second thermal conductivity different than the first thermal conductivity. A method of forming a switch includes forming a heater layer, forming a phase change material (PCM) layer on the heater layer, and forming a spreader layer in proximity to the PCM layer, such that the spreader layer includes a central region with a first thermal conductivity and an edge region with a second thermal conductivity different than the first thermal conductivity.

Abstract: A semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (WoW) configuration. A through silicon via (TSV) structure may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.

Abstract: A method for treating wastewater containing ertriazole compounds is provided. Hypochlorous acid (HOCl) having a neutral to slightly acidic pH value is added to the wastewater containing triazole compounds for reaction, thereby effectively reacting more than 90% of triazole compounds.

Abstract: An embodiment phase change material (PCM) switch may include a PCM element having a first electrode and a second electrode, a heating element coupled to a first side of the PCM element, and a heat spreader formed on a second side of the PCM element opposite to the heating element. The PCM element may include a phase change material that switches from an electrically conducting phase to an electrically insulating phase by application of a heat pulse provided by the heating element. The first electrode, the second electrode, the PCM element, and the heat spreader may be configured as an RF switch that blocks RF signals when the phase change material element is the electrically insulating phase and conducts RF signals when the when the phase change material element is in the electrically conducting phase. The heat spreader may be electrically isolated from the heating element and the PCM element.

Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.

Abstract: Provided are ferroelectric tunnel junction (FTJ) structures, memory devices, and methods for fabricating such structures and devices. An FTJ structure includes a first electrode, a ferroelectric material layer, and a catalytic metal layer in contact with the ferroelectric material layer.

Abstract: A semiconductor structure includes an inductive metal line located in a dielectric material layer that overlies a semiconductor substrate and laterally encloses a first area; and an array of first ferromagnetic plates including a first ferromagnetic material and overlying or underlying the inductive metal line. For any first point that is selected within volumes of the first ferromagnetic plates, a respective second point exists within a horizontal surface of the inductive metal line such that a line connecting the first point and the second point is vertical or has a respective first taper angle that is less than 20 degrees with respective to a vertical direction. The magnetic field passing through the first ferromagnetic plates is applied generally along a hard direction of magnetization and the hysteresis effect is minimized.

Abstract: A memory device includes a transistor device; a memory cell electrically coupled to a source or drain of the transistor device, wherein the memory cell includes an FJT structure; and a heating structure formed around the memory cell on a plurality of sides. The FJT structure includes a first conductive electrode having sidewalls that extend in a vertical direction to a first elevation level, a second conductive electrode having sidewalls that extend in the vertical direction to the first elevation level, and a switching barrier disposed between the first conductive electrode and the second conductive electrode and having sidewalls that extend in the vertical direction to the first elevation level, wherein the vertically extending sidewalls of the first conductive electrode, the second conductive electrode, and the switching barrier terminate at the first elevation level. The switching barrier includes ferroelectric (Fe) material that may be polarized to store information.

Abstract: A selector structure may include a bottom electrode including a bottom low thermal conductivity (LTC) metal and a first bottom high thermal conductivity (HTC) metal, a first switching film on the bottom electrode and having an electrical resistivity switchable by an electric field, and a first top electrode on the first switching film and including a first top low thermal conductivity (LTC) metal and a first top high thermal conductivity (HTC) metal.

Abstract: A phase-change material (PCM) switching device includes: a base dielectric layer over a semiconductor substrate; a first heater element disposed on the base dielectric layer, the first heater element comprising a first metal element characterized by a first coefficient of thermal expansion (CTE); a second heater element disposed on the first heater element, the second heater element comprising a second metal element characterized by a second CTE larger than the first CTE; a first metal pad and a second metal pad; and a PCM region comprising a PCM operable to switch between an amorphous state and a crystalline state in response to heat generated by the first heater element and the second heater element, wherein the PCM region is disposed above a top surface of the second heater element, and an air gap surrounds the first heater element and the second heater element from three sides.

Abstract: A phase change device includes a substrate with a top surface. A heater structure is disposed on the substrate. The heater structure has first and second sidewalls on opposite sides of the heater structure. A phase change element is disposed over the heater structure. The phase change element includes three connected portions. A first portion is disposed over the heater structure. A second portion is disposed over the first sidewall of the heater structure. A third portion is over a first portion of the top surface of the substrate adjacent to and spaced apart from the first sidewall of the heater structure.

Abstract: A semiconductor structure comprising a first electrode, a second electrode, a phase-change material (PCM) line in contact with and positioned between the first electrode and the second electrode, at least two heater lines positioned between the first electrode and the second electrode, and an isolation layer positioned between the PCM line and the at least two heater lines is provided. A method of forming a semiconductor structure is provided, the method including forming a dielectric isolation layer having a planar top surface over a substrate, forming at least two heater lines over the planar top surface, forming at least one heater-capping dielectric plate over the at least two heater lines, forming a phase-change material (PCM) line over the at least one heater-capping dielectric plate, forming a first electrode and a second electrode, and forming a PCM-capping dielectric plate over the PCM line.

Abstract: A pyroelectric generator may be included in the same semiconductor device as a radio frequency (RF) switch (e.g., a phase-change material (PCM) RF switch and/or other types of RF switch). The pyroelectric generator includes a pyroelectric material layer between two electrodes. The pyroelectric generator is configured to scavenge thermal energy that is generated during the operation of the RF switch, and to convert the thermal energy into electrical energy that may be stored and reused.

Abstract: A phase-change material (PCM) switching device is provided. The PCM switching device includes: a base dielectric layer over a semiconductor substrate; a heater element embedded in the base dielectric layer, the heater element comprising a first metal element and configured to generate heat in response to a current flowing therethrough; a self-aligned dielectric layer disposed on the heater element, wherein the self-aligned dielectric layer comprises one of an oxide of the first metal element and a nitride of the first metal element, and the self-aligned dielectric layer is horizontally aligned with the heater element; a PCM region disposed on the self-aligned dielectric layer, wherein the PCM region comprises a PCM operable to switch between an amorphous state and a crystalline state in response to the heat generated by the heater element; and two metal pads electrically connected to the PCM region.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, and a heater element on the semiconductor substrate, the heater element configured to generate heat in response to a current flowing therethrough. The semiconductor device also includes a conductor material having a programmable conductivity, and an insulator layer between the heater element and the conductor material, where the conductor material is configured to be programmed by applying one or more voltage differences to one or more of the heater element and the conductor material, and where a capacitance between the conductor material and the heater element is configured to be controlled by the voltage differences such that the capacitance is lower while the conductor material is being programmed than while the conductor material is not being programmed.