Abstract: The present disclosure provides a bias clamp circuit, which includes a plurality of switchable clamp voltage paths, configured to selectively clamp a gate bias voltage of a vulnerable circuit to a first voltage or a second voltage based on whether a reliability acceleration test is performed on the vulnerable circuit or not. The second voltage is higher than the first voltage.

Abstract: A one-time programmable (OTP) memory includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, each memory cell of the plurality of memory cells including a first terminal coupled to a bit line of the plurality of bit lines, a second terminal coupled to a word line of the plurality of word lines, and a selector coupled between the first terminal and the second terminal and having a threshold voltage that is alterable by an electric current.

Abstract: A semiconductor structure includes a first electrode, a second electrode and a dielectric layer. The second electrode is disposed over the first electrode. The dielectric layer is disposed between the first electrode and the second electrode, and is configured to store information, wherein a bandgap at a first surface of the dielectric layer facing the first electrode is greater than a bandgap at a second surface of the dielectric layer facing the second electrode. A method of manufacturing the semiconductor structure is also provided.

Abstract: A semiconductor device includes a radio frequency (RF) switch and a shielding layer between the RF switch and a semiconductor substrate of the semiconductor device. The shielding layer suppresses electric field emissions and/or magnetic field emissions generated by the RF switch, which prevents, minimizes, and/or otherwise reduces the likelihood of the electric field emissions and/or the magnetic field emissions causing a parasitic current to be induced in the semiconductor substrate. In this way, the shielding layer described herein reduces, minimizes, and/or prevents harmonic distortion in the operation of the RF switch. This enables the RF switch to maintain linear operation, which enables more accurate and faster switching for the RF circuit.

Abstract: Phase change material (PCM) switches and methods of fabrication thereof that provide improved thermal confinement within a phase change material layer. A PCM switch may include a dielectric capping layer between a heater pad and the phase change material layer of the PCM switch that is laterally-confined such opposing sides of the dielectric capping layer the heater pad may form continuous surfaces extending transverse to the signal transmission pathway across the PCM switch. Heat transfer from the heater pad through the dielectric capping layer to the phase change material layer may be predominantly vertical, with minimal thermal dissipation along a lateral direction. The localized heating of the phase change material may improve the efficiency of the PCM switch enabling lower bias voltages, minimize the formation of regions of intermediate resistivity in the PCM switch, and improve the parasitic capacitance characteristics of the PCM switch.

Abstract: A method is provided. The method comprises: providing a semiconductor substrate; depositing a heater element over the semiconductor substrate; depositing an insulator layer on the heater element; depositing a conductor material having a programmable conductivity on the insulator layer, wherein a capacitance between the conductor material and the heater element is configured to be controlled such that the capacitance is lower while the conductor material is being programmed than while the conductor material is not being programmed; depositing a dielectric layer on the conductor material; patterning and etching a first opening and a second opening in the dielectric layer; and depositing a first via in the first opening and a second via in the second opening.

Abstract: Various embodiments of the present application are directed towards an integrated chip. The integrated chip includes a first fin structure and a second fin structure disposed on a base region of a substrate. A first source/drain region is disposed on the first fin structure. A second source/drain region is disposed on the second fin structure. A gate structure overlies the base region of the substrate and is spaced laterally between the first and second fin structures. A bottom surface of the gate structure is disposed below bottoms of the first and second source/drain regions.

Abstract: Some embodiments relate to a memory cell, including: a write transistor on a substrate and comprising a first gate terminal, a first source/drain region, and a second source/drain region coupled to a storage node; a first read transistor on the substrate and comprising a second gate terminal coupled to the storage node and a gate dielectric with a first capacitance; and a capacitor spaced from the first read transistor and the write transistor and further separated from the substrate by the first read transistor and the write transistor, wherein the capacitor is coupled to the storage node and has a second capacitance that is over twice the first capacitance.

Abstract: The present disclosure relates to an integrated chip including a first metal layer over a substrate. A second metal layer is over the first metal layer. An ionic crystal layer is between the first metal layer and the second metal layer. A metal oxide layer is between the first metal layer and the second metal layer. The first metal layer, the second metal layer, the ionic crystal layer, and the metal oxide layer are over a transistor device that is arranged along the substrate.

Abstract: A neural network circuit includes an input neuron layer comprises a plurality of first neurons. A hidden neuron layer includes a plurality of second neurons, wherein each of the second neurons comprises a probabilistic bit having a time-varying resistance. The probabilistic bit is a magnetic tunnel junction structure comprises a pinned layer, a free layer, and a tunneling barrier layer between the pinned layer and the free layer. A weight matrix comprising a plurality of synapse units, each of the synapse units connecting one of the plurality of first neurons to a corresponding one of the plurality of first neurons.

Abstract: A device structure includes a first electrode overlying a substrate; a node dielectric contacting the first electrode and including a dielectric material having a dielectric constant greater than 30; and a second electrode contacting the node dielectric. A first one of the first electrode and the second electrode includes a first catalytic metal plate in direct contact with the node dielectric and having a first electronegativity that is not greater than an electronegativity of molybdenum.

Abstract: One embodiment of the present disclosure provides an optical device which includes a waveguide and a light modulator. The light modulator includes a phase-change material and is in direct contact with an outer surface of the waveguide. The optical device also includes a thermal conducting member. The thermal conducting member is positioned on the light modulating member. The optical device further includes a heating member. The heating member is placed on the thermal conducting member and is distant away from the light modulator and the waveguide. The heat produced from the heating member is transferred to the light modulator through the thermal conducting member thereby inducing a phase transition of the light modulator.

Abstract: Phase change material (PCM) switches and methods of fabrication thereof that provide improved thermal confinement within a phase change material layer. A PCM switch may include a dielectric capping layer between a heater pad and the phase change material layer of the PCM switch that is laterally-confined such opposing sides of the dielectric capping layer the heater pad may form continuous surfaces extending transverse to the signal transmission pathway across the PCM switch. Heat transfer from the heater pad through the dielectric capping layer to the phase change material layer may be predominantly vertical, with minimal thermal dissipation along a lateral direction. The localized heating of the phase change material may improve the efficiency of the PCM switch enabling lower bias voltages, minimize the formation of regions of intermediate resistivity in the PCM switch, and improve the parasitic capacitance characteristics of the PCM switch.

Abstract: One embodiment of the present disclosure provides an optical device which includes a waveguide and a light modulator. The light modulator comprising a bridge segment positioned on the waveguide, wherein the bridge segment comprises a phase-change material. The optical device also includes a heating member. The heating member includes an intermediate segment and two electric contact segments. The intermediate segment is in direct contact with the bridge segment of the light modulator. The two electric contact segments are connected to two ends of the intermediate segment, wherein heat produced from the heating member is directly transferred to the bridge segment of the light modulator thereby inducing a phase transition thereof.

Abstract: A semiconductor structure includes a ferroelectric layer and a semiconductor layer. Thee ferroelectric layer has a first surface and a second surface opposite to the first surface. The semiconductor layer is formed on one of the first surface and the second surface.

Abstract: A memory device is provided in various embodiments. The memory device, in those embodiments, has an ovonic threshold switching (OTS) selector comprising multiple layers of OTS materials to achieve a low leakage current and as well as relatively low threshold voltage for the OTS selector. The multiple layers can have at least one layer of low bandgap OTS material and at least one layer of high bandgap OTS material.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, and a heater element on the semiconductor substrate, the heater element configured to generate heat in response to a current flowing therethrough. The semiconductor device also includes a conductor material having a programmable conductivity, and an insulator layer between the heater element and the conductor material, where the conductor material is configured to be programmed by applying one or more voltage differences to one or more of the heater element and the conductor material, and where a capacitance between the conductor material and the heater element is configured to be controlled by the voltage differences such that the capacitance is lower while the conductor material is being programmed than while the conductor material is not being programmed.

Abstract: A method according to the present disclosure includes forming a bottom electrode layer over a substrate, forming an insulator layer over the bottom electrode layer, depositing a semiconductor layer over the bottom electrode layer, depositing a ferroelectric layer over the semiconductor layer, forming a top electrode layer over the ferroelectric layer, and patterning the bottom electrode layer, the insulator layer, the semiconductor layer, the ferroelectric layer, and the top electrode layer to form a memory stack. The semiconductor layer includes a plurality of portions with different thicknesses.

Abstract: In some embodiments, the present disclosure provides an integrated chip including a first electrode made of a metal; a second electrode disposed over the first electrode; a ferroelectric layer between the first and second electrodes; and an interfacial layer separating the ferroelectric layer and the first electrode, the interfacial layer comprising a semiconductor material and configured to space the first electrode from the ferroelectric layer.

Abstract: Structures and fabrication methods are disclosed wherein a switch and a capacitor are fabricated sharing the same process flow without the use of an extra mask. A first capacitor electrode is formed in parallel in the same metal layer using the same mask as a component of the PCM switch (e.g., a PCM switch heater electrode). A second capacitor electrode is formed in parallel in the same metal layer using the same mask as another component of the PCM switch (e.g., a PCM switch input pad or a PCM switch heat spreader). The capacitor insulator is formed in parallel in the same layer using the same mask as a PCM switch insulator (e.g., TBR or insulator between heat spreader and PCM layer).