Abstract: An LED package structure includes three LED dies and a black sealant layer. Each of the LED dies is provided with a bottom surface, a top surface, and a peripheral wall. The bottom surface and the top surface are opposite to each other, and the peripheral wall is connected to the top surface and the bottom surface. The black sealant layer is coated among the three LED dies and coats the peripheral wall of each of the LED dies. The black sealant layer is provided with a joint surface. The joint surface is coplanar with the bottom surface of each of the LED dies. The black sealant layer does not cover the top surface of each of the LED dies. Also provided is an LED display apparatus which has a better visual taste.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, and a heater element on the semiconductor substrate, the heater element configured to generate heat in response to a current flowing therethrough. The semiconductor device also includes a conductor material having a programmable conductivity, and an insulator layer between the heater element and the conductor material, where the conductor material is configured to be programmed by applying one or more voltage differences to one or more of the heater element and the conductor material, and where a capacitance between the conductor material and the heater element is configured to be controlled by the voltage differences such that the capacitance is lower while the conductor material is being programmed than while the conductor material is not being programmed.

Abstract: A method according to the present disclosure includes forming a bottom electrode layer over a substrate, forming an insulator layer over the bottom electrode layer, depositing a semiconductor layer over the bottom electrode layer, depositing a ferroelectric layer over the semiconductor layer, forming a top electrode layer over the ferroelectric layer, and patterning the bottom electrode layer, the insulator layer, the semiconductor layer, the ferroelectric layer, and the top electrode layer to form a memory stack. The semiconductor layer includes a plurality of portions with different thicknesses.

Abstract: In some embodiments, the present disclosure provides an integrated chip including a first electrode made of a metal; a second electrode disposed over the first electrode; a ferroelectric layer between the first and second electrodes; and an interfacial layer separating the ferroelectric layer and the first electrode, the interfacial layer comprising a semiconductor material and configured to space the first electrode from the ferroelectric layer.

Abstract: A device structure includes a first series connection of a first phase change memory (PCM) switch and a second PCM switch. The first PCM switch includes a first heater line, a first PCM line, and a first contact electrode and a second contact electrode located on the first heater line. The second PCM switch includes a second heater line, a second PCM line, and a third contact electrode and a fourth contact electrode located on the second heater line. The second contact electrode is electrically connected to the third contact electrode. The fourth contact electrode is electrically grounded. One of the first contact electrode and the second contact electrode includes an radio-frequency (RF) signal input port. Another of the first contact electrode and the second contact electrode comprises an RF signal output port. The device structure may function as a combination PCM switch that decreases noise level during signal transmission.

Abstract: Structures and fabrication methods are disclosed wherein a switch and a capacitor are fabricated sharing the same process flow without the use of an extra mask. A first capacitor electrode is formed in parallel in the same metal layer using the same mask as a component of the PCM switch (e.g., a PCM switch heater electrode). A second capacitor electrode is formed in parallel in the same metal layer using the same mask as another component of the PCM switch (e.g., a PCM switch input pad or a PCM switch heat spreader). The capacitor insulator is formed in parallel in the same layer using the same mask as a PCM switch insulator (e.g., TBR or insulator between heat spreader and PCM layer).

Abstract: An embodiment phase change material switch may include a first phase change material element, a second phase change material element, a first conductor electrically connected to a first end of each of the first phase change material element and the second phase change material element such that the first conductor is configured as a first terminal of an electrical circuit having a parallel configuration, a second conductor electrically connected to a second end of each of the first phase change material element and the second phase change material element such that the second conductor is configured as a second terminal of the electrical circuit having the parallel configuration, and a heating device coupled to the first phase change material element and to the second phase change material element and configured to supply a heat pulse to the first phase change material element and to the second phase change material element.

Abstract: A semiconductor may include a handle substrate, a semiconductor material layer on which semiconductor devices, metal interconnect structures, dielectric material layers, and an inductor structure are located, and a patterned magnetic shielding layer including at least one portion of a ferromagnetic material having relative permeability of at least 20 and disposed between the semiconductor material layer and the handle substrate and reducing electromagnetic coupling between the inductor structure and the handle substrate.

Abstract: A device structure includes semiconductor devices located on a substrate; metal interconnect structures located in dielectric material layers overlying the semiconductor devices; and a non-Ohmic voltage-triggered switch including a first switch electrode that is electrically connected to one of the semiconductor devices through a subset of the metal interconnect structures, a second switch electrode, and a non-Ohmic switching material portion providing a non-Ohmic current-voltage characteristics and in contact with the first switch electrode and the second switch electrode. The non-Ohmic voltage-triggered switch may be used as an electrostatic discharge (ESD) switch.

Abstract: A semiconductor structure according to the present disclosure includes a conductive feature in a top portion of a substrate, a bottom electrode layer over and in electrical coupling with the conductive feature, an insulator layer over the bottom electrode layer, a semiconductor layer over the insulator layer, a ferroelectric layer over the semiconductor layer, and a top electrode layer over the ferroelectric layer. The semiconductor layer includes a plurality of portions with different thicknesses.

Abstract: An embodiment phase change material (PCM) switch may include a phase change material element, a first electrode, a second electrode, and a direct heating element including an ionic resistance change material contacting the phase change material element. The phase change material element may include a phase change material that switches from an electrically conducting phase to an electrically insulating phase or from an electrically insulating phase to an electrically conducting phase by application of a heat pulse generated by the heating element. The PCM switch may further include a switching electrode contacting the ionic resistance change material such that the ionic resistance change material may be switched from a high resistance to a low resistance state by application of voltages to the first electrode, the second electrode, and the switching electrode. Electrical currents within the ionic resistance change material may generate heat that switches the phase change material element.

Abstract: A device structure includes a voltage regulator circuit, which includes: a first semiconductor die including a pulse width modulation (PWM) circuit and connected to a PWM voltage output node at which a pulsed voltage output is generated; and a series connection of an inductor and a parallel connection circuit, the parallel connection circuit including a parallel connection of capacitor-switch assemblies. A first end node of the series connection is connected to the PWM voltage output node; a second end node of the series connection is connected to electrical ground; each of the capacitor-switch assemblies includes a respective series connection of a respective capacitor and a respective switch; and each switch within the capacitor-switch assemblies is located within the first semiconductor die.

Abstract: A device structure includes a parallel connection of capacitor-switch assemblies located over a substrate. The capacitor-switch assemblies include a first capacitor-switch assembly that includes a first series connection of a first capacitor and a first non-Ohmic switching device, which has a first threshold voltage and includes a first primary switch electrode, a first secondary switch electrode, and a first non-Ohmic switching material portion. The capacitor switch assemblies further include a second capacitor-switch assembly that includes a second series connection of a second capacitor and a second non-Ohmic switching device, which has a second threshold voltage and includes a second primary switch electrode, a second secondary switch electrode, and a second non-Ohmic switching material portion. The second threshold voltage is different from the first threshold voltage. The non-Ohmic switching devices may be conditionally turned on depending on a magnitude of applied voltage spikes.

Abstract: The present disclosure relates to an integrated chip including a first metal layer over a substrate. A second metal layer is over the first metal layer. An ionic crystal layer is between the first metal layer and the second metal layer. A metal oxide layer is between the first metal layer and the second metal layer. The first metal layer, the second metal layer, the ionic crystal layer, and the metal oxide layer are over a transistor device that is arranged along the substrate.

Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device comprising a chimney seed structure. A ferroelectric layer overlies a bottom electrode layer, and a top electrode layer overlies the ferroelectric layer. The top electrode layer, the ferroelectric layer, and the bottom electrode layer form a plurality of memory cells, and a dielectric wall extends through the top electrode layer and segments the top electrode layer into a plurality top electrodes individual to the memory cells. The chimney seed structure underlies the ferroelectric layer and extends through the bottom electrode layer from the ferroelectric layer. The chimney seed structure is configured to seed ferroelectric crystalline growth in the ferroelectric layer to allow the ferroelectric layer to achieve a large remanent polarization with a small thickness. The small thickness increases read speeds, while the large remanent polarization increases a read window and hence reliability.

Abstract: A semiconductor structure may be located over a substrate, and may include a parallel connection of a first component and a second component. The first component includes a series connection of a diode and a capacitor that is selected from a metal-ferroelectric-metal capacitor and a metal-antiferroelectric-metal capacitor. The second component includes a battery structure. The semiconductor structure may be used as a combination of an energy harvesting device and an energy storage structure that utilizes heat from adjacent semiconductor devices or from other heat sources.

Abstract: A resistive random access memory (ReRAM) apparatus is provided. The ReRAM apparatus includes a plurality of memory cells, each of the memory cells comprises a transistor and a resistor; a bit line connected to a first terminal of the resistor of each of the memory cells; a local source line connected to a source electrode of the transistor of each of the memory cells; and a driving cell connected between the local source line and a global source line. A method for operating the ReRAM apparatus is also provided.

Abstract: Device structures and methods for forming the same are provided. A semiconductor structure according to the present disclosure includes a first electrode and a second electrode disposed over a substrate, a heating element disposed over the substrate, a phase-change material layer disposed over the substrate, and an insulator disposed vertically between the heating element and the phase-change material layer. The phase-change material layer includes at least a first segment and a second segment separated from the first segment. Each of the first and second segments overlaps the heating element in a top view. Each of the first and second segments is electrically connected with both the first and second electrodes.

Abstract: A semiconductor structure may include semiconductor devices located on a substrate, metal interconnect structures that are located within dielectric material layers overlying the semiconductor devices and are electrically connected to the semiconductor devices, and an energy harvesting device located over the metal interconnect structures and comprising a Schottky barrier diode, a first diode electrode located on a first side of the Schottky barrier diode, and a second diode electrode connected to a second side of the Schottky barrier diode

Abstract: A semiconductor device includes a first film, a second film, and a third film that each include a phase change material (PCM) and are arranged with respect to one another along a first lateral direction. The semiconductor device includes a first metal pad, a second metal pad, a third metal pad, and a fourth metal pad. The first and second metal pads are disposed over ends of the first film, respectively, the second and third metal pads are disposed over ends of the second film, respectively, and the third and fourth metal pads are disposed over ends of the third film, respectively. The semiconductor device includes a first heater, a second heater, and a third heater, respectively disposed below the first film, the second film, and the third film.