Patents by Inventor Kuo-Feng LIN

Kuo-Feng LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170025458
    Abstract: An image sensor includes a sensing layer, a number of filter units, and a grid structure. The filter units are disposed on the sensing layer. The grid structure is disposed on the sensing layer and surrounding each of the filter units. The grid structure includes a first partition wall disposed on the sensing layer and located between two adjacent filter units, and a second partition wall disposed on the first partition wall located between the two adjacent filter units. The refractive index of the first partition wall is less than the refractive index of the second partition wall.
    Type: Application
    Filed: July 20, 2015
    Publication date: January 26, 2017
    Inventors: KUO-FENG LIN, WU-CHENG KUO, CHUNG-HAO LIN, YU-KUN HSIAO
  • Patent number: 9178107
    Abstract: A method for fabricating a wafer-level light emitting diode structure is provided. The method includes: providing a substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate; subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a first depressed portion, a second depressed portion, a stacked structure disposed on the second depressed portion and a remained first semiconductor layer disposed on the depressed portion, wherein the stacked structure comprises a patterned second semiconductor layer, a patterned emitting layer, and a patterned first semiconductor layer; forming a first electrode on the remained first semiconductor layer of the first depressed portion; and forming a second electrode correspondingly disposed on the patterned second semiconductor layer of the second depressed portion.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: November 3, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Yao-Jun Tsai, Chen-Peng Hsu, Kuo-Feng Lin, Hsun-Chih Liu, Hung-Lieh Hu, Chien-Jen Sun
  • Patent number: 8759865
    Abstract: A light emitting diode chip, a light emitting diode package structure and a method for forming the same are provided. The light emitting diode chip includes a bonding layer, which has a plurality of voids, or a minimum horizontal distance between a surrounding boundary of the light emitting diode chip and the bonding layer is larger than 0. The light emitting diode chip, the light emitting diode package structure and the method may improve the product yields and enhance the light emitting efficiency.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: June 24, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Yao-Jun Tsai, Chen-Peng Hsu, Kuo-Feng Lin, Hsun-Chih Liu, Ji-Feng Chen, Hung-Lieh Hu, Chien-Jen Sun
  • Publication number: 20130087823
    Abstract: A light emitting diode chip, a light emitting diode package structure and a method for forming the same are provided. The light emitting diode chip includes a bonding layer, which has a plurality of voids, or a minimum horizontal distance between a surrounding boundary of the light emitting diode chip and the bonding layer is larger than 0. The light emitting diode chip, the light emitting diode package structure and the method may improve the product yields and enhance the light emitting efficiency.
    Type: Application
    Filed: August 3, 2011
    Publication date: April 11, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yao-Jun Tsai, Chen-Peng Hsu, Kuo-Feng Lin, Hsun-Chin Liu, Ji-Feng Chen, Hung-Lieh Hu, Chien-Jen Sun
  • Publication number: 20120034714
    Abstract: A method for fabricating a wafer-level light emitting diode structure is provided. The method includes: providing a substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate; subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a first depressed portion, a second depressed portion, a stacked structure disposed on the second depressed portion and a remained first semiconductor layer disposed on the depressed portion, wherein the stacked structure comprises a patterned second semiconductor layer, a patterned emitting layer, and a patterned first semiconductor layer; forming a first electrode on the remained first semiconductor layer of the first depressed portion; and forming a second electrode correspondingly disposed on the patterned second semiconductor layer of the second depressed portion.
    Type: Application
    Filed: August 3, 2011
    Publication date: February 9, 2012
    Applicant: INDUTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yao-Jun TSAI, Chen-Peng HSU, Kuo-Feng LIN, Hsun-Chih LIU, Hung-Lieh HU, Chien-Jen SUN