Patents by Inventor Kuo-Hsiu Wei

Kuo-Hsiu Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10957587
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a conductive feature over a semiconductor substrate and forming a dielectric layer over the conductive feature. The method also includes forming an opening in the dielectric layer to expose the conductive feature. The method further includes forming a conductive material to overfill the opening. In addition, the method includes thinning the conductive material using a chemical mechanical polishing process. A slurry used in the chemical mechanical polishing process includes an iron-containing oxidizer that oxidizes a portion of the conductive material.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Chieh Wu, Kuo-Hsiu Wei, Kei-Wei Chen, Tang-Kuei Chang, Chia Hsuan Lee, Jian-Ci Lin
  • Patent number: 10643892
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Publication number: 20200043786
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a conductive feature over a semiconductor substrate and forming a dielectric layer over the conductive feature. The method also includes forming an opening in the dielectric layer to expose the conductive feature. The method further includes forming a conductive material to overfill the opening. In addition, the method includes thinning the conductive material using a chemical mechanical polishing process. A slurry used in the chemical mechanical polishing process includes an iron-containing oxidizer that oxidizes a portion of the conductive material.
    Type: Application
    Filed: June 24, 2019
    Publication date: February 6, 2020
    Inventors: Li-Chieh Wu, Kuo-Hsiu Wei, Kei-Wei Chen, Tang-Kuei Chang, Chia Hsuan Lee, Jian-Ci Lin
  • Publication number: 20190385909
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Application
    Filed: August 30, 2019
    Publication date: December 19, 2019
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Publication number: 20190371664
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Publication number: 20180337113
    Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a gate structure separating source and drain (S/D) features. The semiconductor device further includes a first dielectric layer formed over the substrate, the first dielectric layer including a first interconnect structure in electrical contact with the S/D features. The semiconductor device further includes an intermediate layer formed over the first dielectric layer, the intermediate layer having a top surface that is substantially coplanar with a top surface of the first interconnect structure. The semiconductor device further includes a second dielectric layer formed over the intermediate layer, the second dielectric layer including a second interconnect structure in electrical contact with the first interconnect structure and a third interconnect structure in electrical contact with the gate structure.
    Type: Application
    Filed: July 27, 2018
    Publication date: November 22, 2018
    Inventors: Jeng Min Liang, Ying-Lang Wang, Kei-Wei Chen, Chi-Wen Liu, Kuo-Hsiu Wei, Kuo-Feng Huang
  • Patent number: 9931726
    Abstract: A wafer edge trimming tool includes an abrasive tape and a holding module configured to hold the abrasive tape against portions of an edge of a rotating wafer during a wafer edge trimming process.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Huai-Tei Yang, Ying-Lang Wang
  • Patent number: 9829806
    Abstract: Methods for processing a substrate having a structure formed thereon and a system for processing a substrate are provided. A substrate is received from first processing equipment, where the first processing equipment has formed the structure on the substrate. A lithography process is performed on the received substrate. The lithography process includes exposing the substrate under an optical condition. The lithography process further includes polishing a backside of the substrate prior to the exposing of the substrate, where the polishing is configured to remove a topographical feature of the backside of the substrate or to remove a contaminant from the backside of the substrate. The substrate does not undergo a cleaning procedure during a period of time between i) the forming of the structure on the substrate, and ii) the exposing of the substrate.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Huai-Tei Yang, Ying-Lang Wang
  • Patent number: 9721984
    Abstract: Semiconductor devices and back side illumination (BSI) sensor manufacturing methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece and forming an integrated circuit on a front side of the workpiece. A grid of a conductive material is formed on a back side of the workpiece using a damascene process.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: August 1, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mu-Han Cheng, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang
  • Patent number: 9676114
    Abstract: A wafer edge trim blade includes a round blade body and at least one slot formed inward from an outside edge of the round blade body. The at least one slot is configured to remove debris generated during wafer edge trimming using the wafer edge trim blade.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: June 13, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Ting Kuo, Kei-Wei Chen, Ying-Lang Wang, Kuo-Hsiu Wei
  • Patent number: 9566683
    Abstract: A method of grinding a wafer includes positioning a wafer beneath a grinding wheel and aligning the wafer and the grinding wheel. The method further includes contacting a grinding surface of an outer base of the grinding wheel with the wafer while rotating at least one of the wafer and the grinding wheel, contacting a grinding surface of an inner frame of the grinding wheel with the wafer while rotating at least one of the wafer and the grinding wheel, without changing the alignment between the wafer and the grinding wheel, and tilting one of the wafer and the grinding wheel relative to the other during at least one of the first and the second contacting steps. The method also includes removing the wafer from the position beneath the grinding wheel.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Chun-Ting Kuo
  • Patent number: 9570311
    Abstract: Methods of thinning a plurality of semiconductor wafers and apparatuses for carrying out the same are disclosed. A grinding module within a set of grinding modules receives and grinds a semiconductor wafer. A polishing module receives the semiconductor wafer from the grinding module and polishes the wafer. The polishing module is configured to polish the semiconductor wafer in less time than the grinding module is configured to grind the corresponding wafer.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: February 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Ting Kuo, Kei-Wei Chen, Ying-Lang Wang, Kuo-Hsiu Wei
  • Patent number: 9339912
    Abstract: An embodiment wafer polishing tool includes an abrasive tape, a polish head holding the abrasive tape, and a rotation module. The rotation module is configured to rotate a wafer during a wafer polishing process, and the polish head is configured to apply pressure to the abrasive tape toward a first surface of the wafer during the wafer polishing process.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Wei-Jen Lo, Ying-Lang Wang
  • Publication number: 20150367475
    Abstract: A grinding wheel comprises an outer base with a first attached grain pad; and an inner frame with a second attached grain pad; and a spindle axis shared by the outer base and the inner frame, wherein at least one of the outer base and the inner frame can move independently along the shared spindle axis; and wherein the outer base, the inner frame, and the shared spindle axis all have a same center. A grinding system comprises an above said grinding wheel, and a wheel head attached to the shared spindle axis, capable of moving vertically, in addition to a motor driving the grinding wheel to spin; and a chuck table for fixing a wafer on top of the chuck table; wherein the grinding wheel overlaps a portion of the chuck table, each capable of spinning to the opposite direction of another.
    Type: Application
    Filed: August 31, 2015
    Publication date: December 24, 2015
    Inventors: Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Chun-Ting Kuo
  • Publication number: 20150262831
    Abstract: Methods for processing a substrate having a structure formed thereon and a system for processing a substrate are provided. A substrate is received from first processing equipment, where the first processing equipment has formed the structure on the substrate. A lithography process is performed on the received substrate. The lithography process includes exposing the substrate under an optical condition. The lithography process further includes polishing a backside of the substrate prior to the exposing of the substrate, where the polishing is configured to remove a topographical feature of the backside of the substrate or to remove a contaminant from the backside of the substrate. The substrate does not undergo a cleaning procedure during a period of time between i) the forming of the structure on the substrate, and ii) the exposing of the substrate.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 17, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: TANG-KUEI CHANG, KUO-HSIU WEI, KEI-WEI CHEN, HUAI-TEI YANG, YING-LANG WANG
  • Patent number: 9120194
    Abstract: A grinding wheel comprises an outer base with a first attached grain pad; and an inner frame with a second attached grain pad; and a spindle axis shared by the outer base and the inner frame, wherein at least one of the outer base and the inner frame can move independently along the shared spindle axis; and wherein the outer base, the inner frame, and the shared spindle axis all have a same center. A grinding system comprises an above said grinding wheel, and a wheel head attached to the shared spindle axis, capable of moving vertically, in addition to a motor driving the grinding wheel to spin; and a chuck table for fixing a wafer on top of the chuck table; wherein the grinding wheel overlaps a portion of the chuck table, each capable of spinning to the opposite direction of another.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Chun-Ting Kuo
  • Patent number: 9064770
    Abstract: A method includes forming top metal lines over a semiconductor substrate, wherein the semiconductor substrate is a portion of a wafer having a bevel. When the top metal lines are exposed, an etchant is supplied on the bevel, wherein regions of the wafer sprayed with the etchant has an inner defining line forming a first ring having a first diameter. A trimming step is performed to trim an edge portion of the wafer, wherein an edge of a remaining portion of the wafer has a second diameter substantially equal to or smaller than the first diameter.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: June 23, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ting Kuo, Kei-Wei Chen, Ying-Lang Wang, Kuo-Hsiu Wei
  • Publication number: 20140024170
    Abstract: A method includes forming top metal lines over a semiconductor substrate, wherein the semiconductor substrate is a portion of a wafer having a bevel. When the top metal lines are exposed, an etchant is supplied on the bevel, wherein regions of the wafer sprayed with the etchant has an inner defining line forming a first ring having a first diameter. A trimming step is performed to trim an edge portion of the wafer, wherein an edge of a remaining portion of the wafer has a second diameter substantially equal to or smaller than the first diameter.
    Type: Application
    Filed: July 17, 2012
    Publication date: January 23, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Ting Kuo, Kei-Wei Chen, Ying-Lang Wang, Kuo-Hsiu Wei
  • Publication number: 20130273686
    Abstract: Semiconductor devices and back side illumination (BSI) sensor manufacturing methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece and forming an integrated circuit on a front side of the workpiece. A grid of a conductive material is formed on a back side of the workpiece using a damascene process.
    Type: Application
    Filed: April 12, 2012
    Publication date: October 17, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mu-Han Cheng, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang
  • Publication number: 20130220090
    Abstract: A wafer edge trim blade includes a round blade body and at least one slot formed inward from an outside edge of the round blade body. The at least one slot is configured to remove debris generated during wafer edge trimming using the wafer edge trim blade.
    Type: Application
    Filed: February 29, 2012
    Publication date: August 29, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Ting KUO, Kei-Wei CHEN, Ying-Lang WANG, Kuo-Hsiu WEI