Patents by Inventor Kuo-Hsiu Wei
Kuo-Hsiu Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180337113Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a gate structure separating source and drain (S/D) features. The semiconductor device further includes a first dielectric layer formed over the substrate, the first dielectric layer including a first interconnect structure in electrical contact with the S/D features. The semiconductor device further includes an intermediate layer formed over the first dielectric layer, the intermediate layer having a top surface that is substantially coplanar with a top surface of the first interconnect structure. The semiconductor device further includes a second dielectric layer formed over the intermediate layer, the second dielectric layer including a second interconnect structure in electrical contact with the first interconnect structure and a third interconnect structure in electrical contact with the gate structure.Type: ApplicationFiled: July 27, 2018Publication date: November 22, 2018Inventors: Jeng Min Liang, Ying-Lang Wang, Kei-Wei Chen, Chi-Wen Liu, Kuo-Hsiu Wei, Kuo-Feng Huang
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Patent number: 9931726Abstract: A wafer edge trimming tool includes an abrasive tape and a holding module configured to hold the abrasive tape against portions of an edge of a rotating wafer during a wafer edge trimming process.Type: GrantFiled: March 15, 2013Date of Patent: April 3, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Huai-Tei Yang, Ying-Lang Wang
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Patent number: 9829806Abstract: Methods for processing a substrate having a structure formed thereon and a system for processing a substrate are provided. A substrate is received from first processing equipment, where the first processing equipment has formed the structure on the substrate. A lithography process is performed on the received substrate. The lithography process includes exposing the substrate under an optical condition. The lithography process further includes polishing a backside of the substrate prior to the exposing of the substrate, where the polishing is configured to remove a topographical feature of the backside of the substrate or to remove a contaminant from the backside of the substrate. The substrate does not undergo a cleaning procedure during a period of time between i) the forming of the structure on the substrate, and ii) the exposing of the substrate.Type: GrantFiled: March 14, 2014Date of Patent: November 28, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Huai-Tei Yang, Ying-Lang Wang
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Patent number: 9721984Abstract: Semiconductor devices and back side illumination (BSI) sensor manufacturing methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece and forming an integrated circuit on a front side of the workpiece. A grid of a conductive material is formed on a back side of the workpiece using a damascene process.Type: GrantFiled: April 12, 2012Date of Patent: August 1, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mu-Han Cheng, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang
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Patent number: 9676114Abstract: A wafer edge trim blade includes a round blade body and at least one slot formed inward from an outside edge of the round blade body. The at least one slot is configured to remove debris generated during wafer edge trimming using the wafer edge trim blade.Type: GrantFiled: February 29, 2012Date of Patent: June 13, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Ting Kuo, Kei-Wei Chen, Ying-Lang Wang, Kuo-Hsiu Wei
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Patent number: 9566683Abstract: A method of grinding a wafer includes positioning a wafer beneath a grinding wheel and aligning the wafer and the grinding wheel. The method further includes contacting a grinding surface of an outer base of the grinding wheel with the wafer while rotating at least one of the wafer and the grinding wheel, contacting a grinding surface of an inner frame of the grinding wheel with the wafer while rotating at least one of the wafer and the grinding wheel, without changing the alignment between the wafer and the grinding wheel, and tilting one of the wafer and the grinding wheel relative to the other during at least one of the first and the second contacting steps. The method also includes removing the wafer from the position beneath the grinding wheel.Type: GrantFiled: August 31, 2015Date of Patent: February 14, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Chun-Ting Kuo
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Patent number: 9570311Abstract: Methods of thinning a plurality of semiconductor wafers and apparatuses for carrying out the same are disclosed. A grinding module within a set of grinding modules receives and grinds a semiconductor wafer. A polishing module receives the semiconductor wafer from the grinding module and polishes the wafer. The polishing module is configured to polish the semiconductor wafer in less time than the grinding module is configured to grind the corresponding wafer.Type: GrantFiled: February 10, 2012Date of Patent: February 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Ting Kuo, Kei-Wei Chen, Ying-Lang Wang, Kuo-Hsiu Wei
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Patent number: 9339912Abstract: An embodiment wafer polishing tool includes an abrasive tape, a polish head holding the abrasive tape, and a rotation module. The rotation module is configured to rotate a wafer during a wafer polishing process, and the polish head is configured to apply pressure to the abrasive tape toward a first surface of the wafer during the wafer polishing process.Type: GrantFiled: March 15, 2013Date of Patent: May 17, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Wei-Jen Lo, Ying-Lang Wang
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Publication number: 20150367475Abstract: A grinding wheel comprises an outer base with a first attached grain pad; and an inner frame with a second attached grain pad; and a spindle axis shared by the outer base and the inner frame, wherein at least one of the outer base and the inner frame can move independently along the shared spindle axis; and wherein the outer base, the inner frame, and the shared spindle axis all have a same center. A grinding system comprises an above said grinding wheel, and a wheel head attached to the shared spindle axis, capable of moving vertically, in addition to a motor driving the grinding wheel to spin; and a chuck table for fixing a wafer on top of the chuck table; wherein the grinding wheel overlaps a portion of the chuck table, each capable of spinning to the opposite direction of another.Type: ApplicationFiled: August 31, 2015Publication date: December 24, 2015Inventors: Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Chun-Ting Kuo
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Publication number: 20150262831Abstract: Methods for processing a substrate having a structure formed thereon and a system for processing a substrate are provided. A substrate is received from first processing equipment, where the first processing equipment has formed the structure on the substrate. A lithography process is performed on the received substrate. The lithography process includes exposing the substrate under an optical condition. The lithography process further includes polishing a backside of the substrate prior to the exposing of the substrate, where the polishing is configured to remove a topographical feature of the backside of the substrate or to remove a contaminant from the backside of the substrate. The substrate does not undergo a cleaning procedure during a period of time between i) the forming of the structure on the substrate, and ii) the exposing of the substrate.Type: ApplicationFiled: March 14, 2014Publication date: September 17, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: TANG-KUEI CHANG, KUO-HSIU WEI, KEI-WEI CHEN, HUAI-TEI YANG, YING-LANG WANG
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Patent number: 9120194Abstract: A grinding wheel comprises an outer base with a first attached grain pad; and an inner frame with a second attached grain pad; and a spindle axis shared by the outer base and the inner frame, wherein at least one of the outer base and the inner frame can move independently along the shared spindle axis; and wherein the outer base, the inner frame, and the shared spindle axis all have a same center. A grinding system comprises an above said grinding wheel, and a wheel head attached to the shared spindle axis, capable of moving vertically, in addition to a motor driving the grinding wheel to spin; and a chuck table for fixing a wafer on top of the chuck table; wherein the grinding wheel overlaps a portion of the chuck table, each capable of spinning to the opposite direction of another.Type: GrantFiled: July 21, 2011Date of Patent: September 1, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Chun-Ting Kuo
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Patent number: 9064770Abstract: A method includes forming top metal lines over a semiconductor substrate, wherein the semiconductor substrate is a portion of a wafer having a bevel. When the top metal lines are exposed, an etchant is supplied on the bevel, wherein regions of the wafer sprayed with the etchant has an inner defining line forming a first ring having a first diameter. A trimming step is performed to trim an edge portion of the wafer, wherein an edge of a remaining portion of the wafer has a second diameter substantially equal to or smaller than the first diameter.Type: GrantFiled: July 17, 2012Date of Patent: June 23, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ting Kuo, Kei-Wei Chen, Ying-Lang Wang, Kuo-Hsiu Wei
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Publication number: 20140024170Abstract: A method includes forming top metal lines over a semiconductor substrate, wherein the semiconductor substrate is a portion of a wafer having a bevel. When the top metal lines are exposed, an etchant is supplied on the bevel, wherein regions of the wafer sprayed with the etchant has an inner defining line forming a first ring having a first diameter. A trimming step is performed to trim an edge portion of the wafer, wherein an edge of a remaining portion of the wafer has a second diameter substantially equal to or smaller than the first diameter.Type: ApplicationFiled: July 17, 2012Publication date: January 23, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Ting Kuo, Kei-Wei Chen, Ying-Lang Wang, Kuo-Hsiu Wei
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Publication number: 20130273686Abstract: Semiconductor devices and back side illumination (BSI) sensor manufacturing methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece and forming an integrated circuit on a front side of the workpiece. A grid of a conductive material is formed on a back side of the workpiece using a damascene process.Type: ApplicationFiled: April 12, 2012Publication date: October 17, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mu-Han Cheng, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang
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Publication number: 20130220090Abstract: A wafer edge trim blade includes a round blade body and at least one slot formed inward from an outside edge of the round blade body. The at least one slot is configured to remove debris generated during wafer edge trimming using the wafer edge trim blade.Type: ApplicationFiled: February 29, 2012Publication date: August 29, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Ting KUO, Kei-Wei CHEN, Ying-Lang WANG, Kuo-Hsiu WEI
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Publication number: 20130210321Abstract: Methods of thinning a plurality of semiconductor wafers and apparatuses for carrying out the same are disclosed. A grinding module within a set of grinding modules receives and grinds a semiconductor wafer. A polishing module receives the semiconductor wafer from the grinding module and polishes the wafer. The polishing module is configured to polish the semiconductor wafer in less time than the grinding module is configured to grind the corresponding wafer.Type: ApplicationFiled: February 10, 2012Publication date: August 15, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Ting KUO, Kei-Wei CHEN, Ying-Lang WANG, Kuo-Hsiu WEI
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Publication number: 20130210172Abstract: A wafer thinning apparatus includes a first metrology tool configured to measure an initial thickness of the wafer. The wafer thinning apparatus further includes a controller connected to the first metrology tool, and configured to determine a polishing time based on the initial thickness, a predetermined thickness and a material removal rate. The wafer thinning apparatus further includes a polishing tool connected to the controller configured to polish the wafer for a period of time equal to the polishing time. The wafer thinning apparatus includes a second metrology tool connected to the controller and the polishing tool, and configured to measure a polished thickness. The controller is configured to update the material removal rate based on the polished thickness, the predetermined thickness and the polishing time.Type: ApplicationFiled: February 10, 2012Publication date: August 15, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yuan-Hsuan Chen, Kei-Wei CHEN, Ying-Lang WANG, Kuo-Hsiu WEI
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Publication number: 20130023188Abstract: A grinding wheel comprises an outer base with a first attached grain pad; and an inner frame with a second attached grain pad; and a spindle axis shared by the outer base and the inner frame, wherein at least one of the outer base and the inner frame can move independently along the shared spindle axis; and wherein the outer base, the inner frame, and the shared spindle axis all have a same center. A grinding system comprises an above said grinding wheel, and a wheel head attached to the shared spindle axis, capable of moving vertically, in addition to a motor driving the grinding wheel to spin; and a chuck table for fixing a wafer on top of the chuck table; wherein the grinding wheel overlaps a portion of the chuck table, each capable of spinning to the opposite direction of another.Type: ApplicationFiled: July 21, 2011Publication date: January 24, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Chun-Ting Kuo
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Publication number: 20120264303Abstract: A metal polishing slurry includes a chemical solution and abrasives characterized by a bimodal or other multimodal distribution of particle sizes or a prevalence of two or more particle sizes or ranges of particle sizes. A method and system for using the slurry in a CMP polishing operation, are also provided.Type: ApplicationFiled: April 15, 2011Publication date: October 18, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kei-Wei CHEN, Kuo-Hsiu WEI, Shih-Chieh CHANG, Ying-Lang WANG
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Patent number: 8049213Abstract: A method of measuring dimensional characteristics includes providing a substrate and forming a reflective layer over the substrate. A dielectric layer is then formed over the reflective layer. The dielectric layer includes a grating pattern and a resistivity test line inset in a transparent region. Radiation is then directed onto the dielectric layer so that some of the radiation is transmitted through the transparent region to the reflective layer. A radiation pattern is then detected from the radiation reflected and scattered by the metal grating pattern. The radiation pattern is analyzed to determine a first dimensional information. Then the resistance of the resistivity test line is measured, and that resistance is analyzed to determine a second dimensional information. The first and second dimensional informations are then compared.Type: GrantFiled: December 18, 2007Date of Patent: November 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Chung Su, Yi-Wei Chiu, Tzu Chan Weng, Yih Song Chiu, Pin Chia Su, Chih-Cherng Jeng, Kuo-Hsiu Wei