Patents by Inventor Kuo-Hui Su

Kuo-Hui Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10937790
    Abstract: A semiconductor device includes a first bit line disposed over a semiconductor substrate. The semiconductor device also includes a capacitor contact and a dielectric structure disposed over the semiconductor substrate and adjacent to the first bit line. The capacitor contact, the dielectric structure and the first bit line are separated from one another by an air gap structure.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 2, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Hui Su
  • Publication number: 20210050355
    Abstract: A semiconductor device includes a first bit line disposed over a semiconductor substrate. The semiconductor device also includes a capacitor contact and a dielectric structure disposed over the semiconductor substrate and adjacent to the first bit line. The capacitor contact, the dielectric structure and the first bit line are separated from one another by an air gap structure.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 18, 2021
    Inventor: Kuo-Hui SU
  • Publication number: 20210036130
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20200395214
    Abstract: A semiconductor structure includes a base layer with a top surface and a plurality of processed areas. A primary pattern is disposed on the top surface of the base layer, wherein the primary pattern has a pattern top surface, a processed area on the pattern top surface, and a sidewall, and the primary pattern has a first critical dimension, and the processed areas are on the part of the top surface of the base layer exposed by the primary pattern. A secondary pattern is disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 17, 2020
    Inventor: KUO-HUI SU
  • Patent number: 10840136
    Abstract: The present disclosure provides a method for preparing a conductive plug. The method includes forming a first conductive structure over a substrate; forming a first dielectric structure over the first conductive structure; transforming a sidewall portion of the first conductive structure into a first dielectric portion; and removing the first dielectric portion such that a width of the first dielectric structure is greater than a width of a remaining portion of the first conductive structure.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: November 17, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Hui Su
  • Publication number: 20200357766
    Abstract: A semiconductor package includes a plurality of intermediate dies and an encapsulant layer. The intermediate dies are stacked on a base die, in which the edge regions of the base die are exposed. The encapsulant layer is disposed to cover side surfaces of the intermediate dies as well as a surface of the exposed edge regions of the base die. The surface of the edge regions of the base die includes an adhesion enhancement layer.
    Type: Application
    Filed: May 9, 2019
    Publication date: November 12, 2020
    Inventor: Kuo-Hui SU
  • Publication number: 20200335486
    Abstract: The present disclosure relates to a semiconductor package and a method for preparing the same. The semiconductor package includes a lower semiconductor layer, an upper semiconductor layer, a fixturing structure, and a molding layer. The lower semiconductor layer includes an attached region and a fixturing region adjacent to the attached region. The upper semiconductor layer is disposed over the attached region. The fixturing structure is disposed adjacent to the upper semiconductor layer. The fixturing structure has at least one fixturing hole, the fixturing hole has an opening corresponding to the fixturing region, and the opening has a first width. The molding layer covers side walls of the upper semiconductor layer. The molding layer has at least one fixturing protrusion extending into the fixturing hole, the fixturing protrusion has a first expanding portion below the opening, and the first expanding portion has a second width greater than the first width.
    Type: Application
    Filed: April 19, 2019
    Publication date: October 22, 2020
    Inventor: KUO-HUI SU
  • Publication number: 20200203157
    Abstract: A method for preparing a multilayer structure includes the following steps. A substrate having a patterned layer is disposed in a reactor. A first metal precursor is introduced into the reactor. A first excess metal precursor is purged from the reactor by pumping out the first excess metal precursor. A first reactant is introduced into the reactor, wherein the first reactant reacts with the first metal precursor to form a first metal-containing layer on the patterned layer. A first excess reactant is purged from the reactor by pumping out the first to excess reactant. A second metal precursor is introduced into the reactor, wherein the second metal precursor is adsorbed on the first metal-containing layer. A second excess metal precursor is purged from the reactor by pumping out the second excess metal precursor. A second reactant is introduced into the reactor, wherein the second reactant reacts with the second metal precursor to form a second metal-containing layer on the first metal-containing layer.
    Type: Application
    Filed: March 25, 2019
    Publication date: June 25, 2020
    Inventor: KUO-HUI SU
  • Patent number: 10651157
    Abstract: A semiconductor device includes a first substrate, a through substrate via, a second substrate, and a bonding structure. The first substrate includes a first dielectric material, and the first dielectric material includes a first conductive pad embedded therein. The through substrate via is formed in the first substrate. The second substrate includes a second dielectric material, the second dielectric material includes a second conductive pad embedded therein, the first dielectric material is different from the second dielectric material, the second conductive pad has a first height, the second dielectric material has a second height, and the first height is less than the second height. The bonding structure is formed between the first substrate and the second substrate, wherein the bonding structure includes the first conductive pad bonded to the second conductive pad and the first dielectric material bonded to the second dielectric material.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: May 12, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Hui Su
  • Patent number: 10641801
    Abstract: A ringer control device includes a power receiving unit, a detection circuit, and a control circuit. The detection circuit is coupled to the power receiving unit and outputs a detection signal. The control circuit is coupled to the detection circuit and includes a trigger unit and a control unit. The trigger unit detects a trigger event. The control unit is coupled to the detection circuit and the trigger unit, and configured to control the detection circuit and determine whether a ringer device is coupled to the power module according to the detection signal, and further determine a category of the ringer device. A control method of the ringer control device is also provided.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: May 5, 2020
    Assignee: Goldtek Technology Co., Ltd.
    Inventors: Ting-Hsuan Su, Kuo-Chuan Yu, Kuang-Hui Su, Wen-Feng Yeh
  • Publication number: 20200072879
    Abstract: A ringer control device includes a power receiving unit, a detection circuit, and a control circuit. The detection circuit is coupled to the power receiving unit and outputs a detection signal. The control circuit is coupled to the detection circuit and includes a trigger unit and a control unit. The trigger unit detects a trigger event. The control unit is coupled to the detection circuit and the trigger unit, and configured to control the detection circuit and determine whether a ringer device is coupled to the power module according to the detection signal, and further determine a category of the ringer device. A control method of the ringer control device is also provided.
    Type: Application
    Filed: January 14, 2019
    Publication date: March 5, 2020
    Inventors: TING-HSUAN SU, KUO-CHUAN YU, KUANG-HUI SU, WEN-FENG YEH
  • Patent number: 9647133
    Abstract: The present invention relates to a novel thin film transistor (TFT) comprising a substrate (100) with a gate electrode layer (101) deposited and patterned thereon and a gate insulator layer (102) deposited on the gate electrode layer and the substrate, characterized in that the transistor further comprises (i) a carrier injection layer (103) arranged above the gate insulator layer, (ii) a source/drain (S/D) electrode layer (104) deposited on the carrier injection layer, and (iii) a semiconductor layer (106), methods for the production of such novel TFTs, devices comprising such TFTs, and to the use of such TFTs.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: May 9, 2017
    Assignee: Evonik Degussa GmbH
    Inventors: Duy Vu Pham, Kuo Hui Su
  • Publication number: 20160284853
    Abstract: The present invention relates to a novel thin film transistor (TFT) comprising a substrate (100) with a gate electrode layer (101) deposited and patterned thereon and a gate insulator layer (102) deposited on the gate electrode layer and the substrate, characterized in that the transistor further comprises (i) a carrier injection layer (103) arranged above the gate insulator layer, (ii) a source/drain (S/D) electrode layer (104) deposited on the carrier injection layer, and (iii) a semiconductor layer (106), methods for the production of such novel TFTs, devices comprising such TFTs, and to the use of such TFTs.
    Type: Application
    Filed: November 13, 2014
    Publication date: September 29, 2016
    Applicant: EVONIK DEGUSSA GMBH
    Inventors: Duy Vu PHAM, Kuo Hui SU
  • Patent number: 9059142
    Abstract: A method for forming a semiconductor device with a vertical gate is disclosed, including providing a substrate, forming a recess in the substrate, forming a gate dielectric layer on a sidewall and a bottom of the recess, forming an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride layer, and forming a gate layer in the recess and on the adhesion layer.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: June 16, 2015
    Assignee: Nanya Technology Corporation
    Inventors: Wen-Ping Liang, Chiang-Hung Lin, Kuo-Hui Su
  • Patent number: 8815735
    Abstract: A semiconductor device comprises a substrate, a dielectric layer, an undoped silicon layer, and a silicon material. The substrate comprises a doped region. The dielectric layer is formed on the substrate and comprises a contact hole, and the contact hole corresponds to the doped region. The undoped silicon layer is formed on the doped region. The silicon material fills the contact hole from the undoped silicon layer.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: August 26, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Yi Jung Chen, Kuo Hui Su, Chiang Hung Lin
  • Patent number: 8772119
    Abstract: A fabricating method of a transistor is provided. A patterned sacrificed layer is formed on a substrate, wherein the patterned sacrificed layer includes a plurality of openings exposing the substrate. By using the patterned sacrificed layer as a mask, a doping process is performed on the substrate, thereby forming a doped source region and a doped drain region in the substrate exposed by the openings. A selective growth process is performed to form a source and a drain on the doped source region and the doped drain region, respectively. The patterned sacrificed layer is removed to expose the substrate between the source and the drain. A gate is formed on the substrate between the source and the drain.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: July 8, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Kuo-Hui Su, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8754531
    Abstract: A through-silicon via (TSV) includes an insulation layer continuously lining a straight sidewall of a recessed via feature; a barrier layer continuously covering the insulation layer; a first portion of a non-continuous seed layer disposed at one end of the recessed via feature; a non-continuous dielectric layer partially covering the straight sidewall of the recessed via feature; and a conductive layer filling the recessed via feature.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: June 17, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Yu-Shan Chiu, Kuo-Hui Su
  • Publication number: 20140021535
    Abstract: A method for forming a semiconductor device with a vertical gate is disclosed, including providing a substrate, forming a recess in the substrate, forming a gate dielectric layer on a sidewall and a bottom of the recess, forming an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride layer, and forming a gate layer in the recess and on the adhesion layer.
    Type: Application
    Filed: July 23, 2012
    Publication date: January 23, 2014
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Wen-Ping Liang, Chiang-Hung Lin, Kuo-Hui Su
  • Publication number: 20140001633
    Abstract: A method for fabricating a copper interconnect structure is disclosed. A substrate having a conductive region is provided. An insulating layer with a via opening is formed on the substrate. The via opening exposes the conductive region. A copper layer is formed on the first insulating layer and fills the via opening by sequentially performing deposition and reflowing processes. A masking layer is formed on the copper layer to cover the via opening. The copper layer uncovered by the masking layer is anisotropically oxidized. The masking layer and the oxidized copper layer are removed by a wet etching process, to form a copper plug in the via opening and a copper wire line on the copper plug. A copper interconnect structure is also disclosed.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 2, 2014
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Chi-Wen Huang, Kuo-Hui Su
  • Publication number: 20130328202
    Abstract: A through silicon via (TSV) structure including a semiconductor substrate; a first inter-metal dielectric (IMD) layer on the semiconductor substrate; a cap layer overlying the IMD layer; a conductive layer extending through the cap layer, the first IMD layer and into the semiconductor substrate; a tungsten film capping a top surface of the conductive layer; a second IMD layer overlying the cap layer and covering the tungsten film; and an interconnect feature in the second IMD layer.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 12, 2013
    Inventors: Chi-Wen Huang, Kuo-Hui Su