Abstract: The present application discloses a method for fabricating a semiconductor device with slanted conductive layers. The method for fabricating a semiconductor device includes providing a substrate, forming a first insulating layer above the substrate, forming first slanted recesses along the first insulating layer, and forming first slanted conductive layers in the first slanted recesses and a top conductive layer covering the first slanted conductive layers.

Abstract: The present application discloses a semiconductor device including a substrate, an active area in the substrate, a first plug positioned above the active area, second plugs positioned above the active area, metal spacers positioned above the first plug and the plurality of second plugs, and air gaps respectively positioned between the plurality of metal spacers. The active area includes a narrow portion having a first width and two side portions having a second width, wherein the narrow portion is disposed between the two side portions, and the first width is less than the second width from a top view.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

Abstract: The present application discloses a semiconductor device including a substrate, an active area in the substrate, a first plug positioned above the active area, second plugs positioned above the active area, metal spacers positioned above the first plug and the plurality of second plugs, and air gaps respectively positioned between the plurality of metal spacers. The active area includes a narrow portion having a first width and two side portions having a second width, wherein the narrow portion is disposed between the two side portions, and the first width is less than the second width from a top view.

Abstract: The present disclosure provides a method for preparing a semiconductor device structure with a fluorine-catching layer. The method includes forming a first dielectric layer over a semiconductor substrate, and forming a first conductive via structure in the first dielectric layer. The method also includes forming a second dielectric layer over the first dielectric layer and covering the first conductive via structure, and forming a fluorine-catching layer over the second dielectric layer. The method further includes forming a third dielectric layer over the fluorine-catching layer, and forming a second conductive via structure in the third dielectric layer, the fluorine-catching layer, and the second dielectric layer.

Abstract: The present disclosure provides a semiconductor device structure with a fluorine-catching layer. The semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure also includes a fluorine-catching layer disposed over the second dielectric layer, and a third dielectric layer disposed over the fluorine-catching layer. The semiconductor device structure further includes a conductive via structure penetrating through the third dielectric layer, the fluorine-catching layer, and the second dielectric layer to contact the first dielectric layer.

Abstract: A method for preparing a semiconductor device structure is provided. The method includes forming a first conductive layer over a semiconductor substrate, and forming a first dielectric layer over the first conductive layer. The first conductive layer includes copper. The method also includes etching the first dielectric layer to form a first opening exposing the first conductive layer, and forming a first lining layer and a first conductive plug in the first opening. The first lining layer includes manganese, the first conductive plug includes copper, and the first conductive plug is surrounded by the first lining layer. The method further includes forming a second conductive layer over the first dielectric layer, the first lining layer and the first conductive layer. The second conductive layer includes copper.

Abstract: The present application discloses a method for fabricating a semiconductor device with metal spacers. The method includes providing a substrate; forming a plurality of plugs above the substrate; forming a plurality of metal spacers above the plurality of plugs; and, forming a plurality of air gaps positioned between the plurality of plugs; wherein the step of forming wherein the plurality of metal spacers comprises forming a first set of metal spacers, forming a second set of metal spacers, forming a third set of metal spacers, and forming a fourth set of metal spacers; wherein the second set of metal spacers is formed between the first set of metal spacers and the third set of metal spacers, and the third set of metal spacers is formed between the second set of metal spacers and the fourth set of metal spacers.

Abstract: A recessed gate structure includes a recessed structure, wherein the recessed structure comprises a substrate with the recess extending into the substrate from a topmost surface of the substrate; a conductive feature, filled in the recess of the recessed structure; a first functional layer, extending between the conductive feature and the recessed structure, and comprising a first element; a second functional layer, extending between the first functional layer and the conductive feature, and comprising a second element; and an interfacial layer, extending along an interface between the first functional layer and the second functional layer, and comprising the first element and the second element.

Abstract: A method for preparing a recessed gate structure includes forming a recessed structure, wherein the recessed structure comprises a substrate with the recess extending into the substrate from a topmost surface of the substrate; forming a first functional layer to at least cover a sidewall of a recess of the recessed structure; forming a second functional layer to cover the first functional layer; performing a rapid thermal treatment to form an interfacial layer extending along an interface between the first functional layer and the second functional layer; and forming a conductive feature to fill up the recess.

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a first energy-sensitive pattern over the target layer. The method also includes forming a lining layer covering the first energy-sensitive pattern, and forming a second energy-sensitive pattern over the lining layer. The first energy-sensitive pattern and the second energy-sensitive pattern are staggered. The method further includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a first energy-sensitive pattern over the target layer. The method also includes performing an energy treating process to transform an upper portion of the first energy-sensitive pattern into a treated portion, forming a lining layer covering the first energy-sensitive pattern, and forming a second energy-sensitive pattern over the lining layer. The first energy-sensitive pattern and the second energy-sensitive pattern are staggered. The method further includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.

Abstract: The present disclosure provides a method for preparing a semiconductor memory device with air gaps for reducing capacitive coupling between a bit line and an adjacent conductive feature. The method includes forming an isolation member defining an active region in a substrate and a doped area in the active region; forming a gate structure in the substrate, wherein the gate structure divides the doped are into a first doped region and a second doped region; forming a bit line structure on the first doped region; forming an air gap adjacent to the bit line structure; forming a capacitor plug on the second doped region and a barrier layer on a sidewall of the capacitor plug; and forming a landing pad on a top portion of the capacitor plug, wherein the landing pad comprises a first silicide layer over the protruding portion and a second silicide layer on a sidewall of the barrier layer.

Abstract: The present disclosure relates to a semiconductor device structure with a serpentine conductive feature and a method for forming the semiconductor device structure. The semiconductor device structure includes a conductive pad disposed in a semiconductor substrate, and a first mask layer disposed over the semiconductor substrate. The semiconductor device structure also includes a second mask layer disposed over the first mask layer. The first mask layer and the second mask layer are made of different materials. The semiconductor device structure further includes a conductive feature penetrating through the first mask layer and the second mask layer to connect to the conductive pad. The conductive feature has a serpentine pattern in a top view.

Abstract: A semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate, and a second conductive layer disposed over the first conductive layer. The semiconductor device structure also includes a first conductive plug disposed between and electrically connecting the first conductive layer and the second conductive layer. The first conductive plug includes copper. The semiconductor device structure further includes a first lining layer surrounding the first conductive plug. The first lining layer includes manganese.

Abstract: The present disclosure relates to a semiconductor device structure with a serpentine conductive feature and a method for forming the semiconductor device structure. The semiconductor device structure includes a conductive pad disposed in a semiconductor substrate, and a first mask layer disposed over the semiconductor substrate. The semiconductor device structure also includes a second mask layer disposed over the first mask layer. The first mask layer and the second mask layer are made of different materials. The semiconductor device structure further includes a conductive feature penetrating through the first mask layer and the second mask layer to connect to the conductive pad. The conductive feature has a serpentine pattern in a top view.

Abstract: The present disclosure provides a semiconductor memory device with air gaps for reducing capacitive coupling between a bit line and an adjacent conductive feature and a method for preparing the semiconductor memory device.

Abstract: The present application discloses a method for preparing a semiconductor device with an air gap structure between conductive structures. The method includes: forming a first bit line, a second bit line, a first capacitor contact and a second capacitor contact over a semiconductor substrate, wherein the first capacitor contact and the second capacitor contact are disposed between the first bit line and the second bit line; forming a first dielectric layer over a sidewall of the first bit line, a sidewall of the second bit line, a sidewall of the first capacitor contact and a sidewall of the second capacitor contact such that an opening is formed and surrounded by the first dielectric layer; filling the opening with a dielectric structure; and removing the first dielectric layer to form an opening structure surrounding the dielectric structure.

Abstract: The present application discloses a semiconductor device with slanted conductive layers and a method for fabricating the semiconductor device with the slanted conductive layers. The semiconductor device includes a substrate, a first insulating layer positioned above the substrate, first slanted conductive layers positioned in the first insulating layer, and a top conductive layer positioned covering the first slanted conductive layers.

Abstract: A semiconductor structure includes a base layer with a top surface and a plurality of processed areas. A primary pattern is disposed on the top surface of the base layer, wherein the primary pattern has a pattern top surface, a processed area on the pattern top surface, and a sidewall, and the primary pattern has a first critical dimension, and the processed areas are on the part of the top surface of the base layer exposed by the primary pattern. A secondary pattern is disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension.