Abstract: The present application discloses a semiconductor device including a substrate, a contact, a landing pad, a bit line, and an air gap. The contact is disposed over the substrate. The landing pad is disposed over the contact. The landing pad includes a plug, a first spacer, and a second spacer. The plug is disposed over and in contact with the contact. The first spacer is disposed over the plug. The second spacer is sandwiching a protruding portion of the plug. The bit line is disposed over the substrate. The air gap is disposed between the contact and the bit line.

Abstract: The present application discloses a semiconductor device including a substrate, a contact, a landing pad, a bit line, and an air gap. The contact is disposed over the substrate. The landing pad is disposed over the contact. The landing pad includes a plug, a first spacer, and a second spacer. The plug is disposed over and in contact with the contact. The first spacer is disposed over the plug. The second spacer is sandwiching a protruding portion of the plug. The bit line is disposed over the substrate. The air gap is disposed between the contact and the bit line.

Abstract: The present application discloses a semiconductor device including a substrate, a contact, a landing pad, a bit line, and an air gap. The contact is disposed over the substrate. The landing pad is disposed over the contact. The landing pad includes a plug, a first spacer, and a second spacer. The plug is disposed over and in contact with the contact. The first spacer is disposed over the plug. The second spacer is sandwiching a protruding portion of the plug. The bit line is disposed over the substrate. The air gap is disposed between the contact and the bit line.

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a first energy-sensitive pattern over the target layer. The method also includes performing an energy treating process to transform an upper portion of the first energy-sensitive pattern into a treated portion, forming a lining layer covering the first energy-sensitive pattern, and forming a second energy-sensitive pattern over the lining layer. The first energy-sensitive pattern and the second energy-sensitive pattern are staggered. The method further includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.

Abstract: The present disclosure provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate; a gate electrode disposed on the substrate; a source region and a drain region disposed in the substrate and on opposite sides of the gate electrode; an isolating layer disposed over the substrate and the gate electrode; a plurality of metal contacts disposed in the gate electrode, the source region, and the drain region; a plurality of conductive plugs disposed in the isolating layer and electrically coupled to the metal contacts; a contact liner surrounding the conductive plugs; and a filling layer disposed in the isolating layer. The filling layer includes boron carbonitride.

Abstract: The present disclosure provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate; a gate electrode disposed on the substrate; a source region and a drain region disposed in the substrate and on opposite sides of the gate electrode; an isolating layer disposed over the substrate and the gate electrode; a plurality of metal contacts disposed in the gate electrode, the source region, and the drain region; a plurality of conductive plugs disposed in the isolating layer and electrically coupled to the metal contacts; a contact liner surrounding the conductive plugs; and a filling layer disposed in the isolating layer. The filling layer includes boron carbonitride.

Abstract: The present disclosure provides a memory device having improved P-N junction and a manufacturing method thereof. The memory device includes a semiconductor substrate having a first surface and defined with an active area under the first surface, a gate structure adjacent to the active area and indented into the semiconductor substrate from the first surface, a doped member extending into the semiconductor substrate and surrounded by the active area, a conductive layer including a first portion extending into the semiconductor substrate from the first surface and a second portion disposed over the doped member and coupled to the first portion, a first insulating layer disposed adjacent to the first portion of the conductive layer and between the doped member and the active area of the semiconductor substrate, a first contact disposed over the conductive layer, and a conductive pillar disposed over the first contact.

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a first energy-sensitive pattern over the target layer. The method also includes forming a lining layer covering the first energy-sensitive pattern, and forming a second energy-sensitive pattern over the lining layer. The first energy-sensitive pattern and the second energy-sensitive pattern are staggered. The method further includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.

Abstract: The present application discloses a semiconductor device including a first die and a second die. The first die includes a first dielectric layer disposed over a first substrate, a second dielectric layer disposed over the first dielectric layer, a first metal layer disposed in the first dielectric layer, and a first conductive via disposed in the second dielectric layer. The first conductive via includes conductive layers and a top conductive layer electrically coupled to the conductive layers. Each of the plurality of conductive layers is extended along a direction. The direction and a top surface of the first die form an acute angle greater than 0 degree. The second die is bonded to the first die by bonding the second conductive via to the first conductive via.

Abstract: The present application discloses a semiconductor device including a first die and a second die. The first die includes a first dielectric layer disposed over a first substrate, a second dielectric layer disposed over the first dielectric layer, a first metal layer disposed in the first dielectric layer, and a first conductive via disposed in the second dielectric layer. The first conductive via includes conductive layers and a top conductive layer electrically coupled to the conductive layers. Each of the plurality of conductive layers are extended along a direction. The direction and a top surface of the first die form an acute angle greater than 0 degrees. The second die is bonded to the first die by bonding the second conductive via to the first conductive via.

Abstract: The present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-sparse region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.

Abstract: The present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-loose region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.

Abstract: A method for preparing a recessed gate structure includes forming a recessed structure, wherein the recessed structure includes a substrate with the recess extending into the substrate from a topmost surface of the substrate; forming a first functional layer to at least cover a sidewall of a recess of the recessed structure; forming a second functional layer to cover the first functional layer; performing a rapid thermal treatment to form an interfacial layer extending along an interface between the first functional layer and the second functional layer; and forming a conductive feature to fill up the recess.

Abstract: The present application discloses a semiconductor device including a substrate, an active area in the substrate, a first plug positioned above the active area, second plugs positioned above the active area, metal spacers positioned above the first plug and the plurality of second plugs, and air gaps respectively positioned between the plurality of metal spacers. The active area includes a narrow portion having a first width and two side portions having a second width, wherein the narrow portion is disposed between the two side portions, and the first width is less than the second width from a top view.

Abstract: A method for preparing a recessed gate structure includes forming a recessed structure, wherein the recessed structure comprises a substrate with the recess extending into the substrate from a topmost surface of the substrate; forming a first functional layer to at least cover a sidewall of a recess of the recessed structure; forming a second functional layer to cover the first functional layer; performing a rapid thermal treatment to form an interfacial layer extending along an interface between the first functional layer and the second functional layer; and forming a conductive feature to fill up the recess.

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a first energy-sensitive pattern over the target layer. The method also includes performing an energy treating process to transform an upper portion of the first energy-sensitive pattern into a treated portion, forming a lining layer covering the first energy-sensitive pattern, and forming a second energy-sensitive pattern over the lining layer. The first energy-sensitive pattern and the second energy-sensitive pattern are staggered. The method further includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a first energy-sensitive pattern over the target layer. The method also includes performing an energy treating process to transform an upper portion of the first energy-sensitive pattern into a treated portion, forming a lining layer covering the first energy-sensitive pattern, and forming a second energy-sensitive pattern over the lining layer. The first energy-sensitive pattern and the second energy-sensitive pattern are staggered. The method further includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a first energy-sensitive pattern over the target layer. The method also includes performing an energy treating process to transform an upper portion of the first energy-sensitive pattern into a treated portion, forming a lining layer covering the first energy-sensitive pattern, and forming a second energy-sensitive pattern over the lining layer. The first energy-sensitive pattern and the second energy-sensitive pattern are staggered. The method further includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.

Abstract: A recessed gate structure includes a recessed structure, wherein the recessed structure comprises a substrate with the recess extending into the substrate from a topmost surface of the substrate; a conductive feature, filled in the recess of the recessed structure; a first functional layer, extending between the conductive feature and the recessed structure, and comprising a first element; a second functional layer, extending between the first functional layer and the conductive feature, and comprising a second element; and an interfacial layer, extending along an interface between the first functional layer and the second functional layer, and comprising the first element and the second element.

Abstract: A method for preparing a recessed gate structure includes forming a recessed structure, wherein the recessed structure includes a substrate with the recess extending into the substrate from a topmost surface of the substrate; forming a first functional layer to at least cover a sidewall of a recess of the recessed structure; forming a second functional layer to cover the first functional layer; performing a rapid thermal treatment to form an interfacial layer extending along an interface between the first functional layer and the second functional layer; and forming a conductive feature to fill up the recess.