Abstract: A method for preparing a semiconductor device structure is provided. The method includes forming a first conductive layer over a semiconductor substrate, and forming a first dielectric layer over the first conductive layer. The first conductive layer includes copper. The method also includes etching the first dielectric layer to form a first opening exposing the first conductive layer, and forming a first lining layer and a first conductive plug in the first opening. The first lining layer includes manganese, the first conductive plug includes copper, and the first conductive plug is surrounded by the first lining layer. The method further includes forming a second conductive layer over the first dielectric layer, the first lining layer and the first conductive layer. The second conductive layer includes copper.

Abstract: A semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate, and a second conductive layer disposed over the first conductive layer. The semiconductor device structure also includes a first conductive plug disposed between and electrically connecting the first conductive layer and the second conductive layer. The first conductive plug includes copper. The semiconductor device structure further includes a first lining layer surrounding the first conductive plug. The first lining layer to includes manganese.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having a plurality of contacts, a plurality of plugs positioned above the plurality of contacts, a plurality of metal spacers positioned above the plurality of plugs; and a plurality of air gaps respectively positioned between the plurality of metal spacers.

Abstract: The present disclosure provides a method for preparing a semiconductor memory device with air gaps for reducing capacitive coupling between a bit line and an adjacent conductive feature. The method includes forming an isolation member defining an active region in a substrate and a doped area in the active region; forming a gate structure in the substrate, wherein the gate structure divides the doped are into a first doped region and a second doped region; forming a bit line structure on the first doped region; forming an air gap adjacent to the bit line structure; forming a capacitor plug on the second doped region and a barrier layer on a sidewall of the capacitor plug; and forming a landing pad on a top portion of the capacitor plug, wherein the landing pad comprises a first silicide layer over the protruding portion and a second silicide layer on a sidewall of the barrier layer.

Abstract: The present application discloses a method for fabricating a semiconductor device with slanted conductive layers. The method for fabricating a semiconductor device includes providing a substrate, forming a first insulating layer above the substrate, forming first slanted recesses along the first insulating layer, and forming first slanted conductive layers in the first slanted recesses and a top conductive layer covering the first slanted conductive layers.

Abstract: The present application discloses a method for fabricating a semiconductor device with metal spacers.

Abstract: The present application discloses a semiconductor device with slanted conductive layers and a method for fabricating the semiconductor device with the slanted conductive layers. The semiconductor device includes a substrate, a first insulating layer positioned above the substrate, first slanted conductive layers positioned in the first insulating layer, and a top conductive layer positioned covering the first slanted conductive layers.

Abstract: A semiconductor structure includes a base layer with a top surface and a plurality of processed areas. A primary pattern is disposed on the top surface of the base layer, wherein the primary pattern has a pattern top surface, a processed area on the pattern top surface, and a sidewall, and the primary pattern has a first critical dimension, and the processed areas are on the part of the top surface of the base layer exposed by the primary pattern. A secondary pattern is disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension.

Abstract: The present disclosure provides a semiconductor memory device with air gaps for reducing capacitive coupling between a bit line and an adjacent conductive feature and a method for preparing the semiconductor memory device.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having first regions and second regions; a plurality of bit line contacts and a plurality of capacitor contacts disposed over the plurality of first regions and second regions; a landing pad disposed over one of the plurality of capacitor contacts, the landing pad comprising a protruding portion of a capacitor plug and a first spacer disposed on a sidewall of the protruding portion; a conductive plug disposed over the landing pad; and a plurality of bit lines disposed over the plurality of bit line contacts; and a capacitor structure disposed over the conductive plug. The capacitor plug includes a plurality of nanowires, a conductive liner disposed over the plurality of nanowires, and a conductor disposed over the conductive liner.

Abstract: The present application discloses a method for preparing a semiconductor device with an air gap structure between conductive structures. The method includes: forming a first bit line, a second bit line, a first capacitor contact and a second capacitor contact over a semiconductor substrate, wherein the first capacitor contact and the second capacitor contact are disposed between the first bit line and the second bit line; forming a first dielectric layer over a sidewall of the first bit line, a sidewall of the second bit line, a sidewall of the first capacitor contact and a sidewall of the second capacitor contact such that an opening is formed and surrounded by the first dielectric layer; filling the opening with a dielectric structure; and removing the first dielectric layer to form an opening structure surrounding the dielectric structure.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having a plurality of contacts, a plurality of plugs positioned above the plurality of contacts, a plurality of metal spacers positioned above the plurality of plugs; and a plurality of air gaps respectively positioned between the plurality of metal spacers.

Abstract: The present disclosure relates to a semiconductor package and a method for preparing the same. The semiconductor package includes a lower semiconductor layer, an upper semiconductor layer, a fixturing structure, and a molding layer. The lower semiconductor layer includes an attached region and a fixturing region adjacent to the attached region. The upper semiconductor layer is disposed over the attached region. The fixturing structure is disposed adjacent to the upper semiconductor layer. The fixturing structure has at least one fixturing hole, the fixturing hole has an opening corresponding to the fixturing region, and the opening has a first width. The molding layer covers side walls of the upper semiconductor layer. The molding layer has at least one fixturing protrusion extending into the fixturing hole, the fixturing protrusion has a first expanding portion below the opening, and the first expanding portion has a second width greater than the first width.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having an upper surface; a plurality of first bit line contacts contacting the upper surface of the substrate and a plurality of second bit line contacts contacting the upper surface of the substrate, wherein the plurality of first bit line contacts and the plurality of second bit line contacts are positioned at different levels along a first direction; an air gap disposed between the first bit line contact and the second bit line contact; a plurality of first bit lines respectively correspondingly positioned on the plurality of first bit line contacts; and a plurality of second bit lines respectively correspondingly positioned on the plurality of first bit line contacts.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having first regions and second regions; a plurality of bit line contacts and a plurality of capacitor contacts disposed over the plurality of first regions and second regions; a landing pad disposed over one of the plurality of capacitor contacts, the landing pad comprising a protruding portion of a capacitor plug and a first spacer disposed on a sidewall of the protruding portion; a conductive plug disposed over the landing pad; and a plurality of bit lines disposed over the plurality of bit line contacts; and a capacitor structure disposed over the conductive plug. The capacitor plug includes a plurality of nanowires, a conductive liner disposed over the plurality of nanowires, and a conductor disposed over the conductive liner.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having an upper surface; a plurality of first bit line contacts contacting the upper surface of the substrate and a plurality of second bit line contacts contacting the upper surface of the substrate, wherein the plurality of first bit line contacts and the plurality of second bit line contacts are positioned at different levels along a first direction; an air gap disposed between the first bit line contact and the second bit line contact; a plurality of first bit lines respectively correspondingly positioned on the plurality of first bit line contacts; and a plurality of second bit lines respectively correspondingly positioned on the plurality of first bit line contacts.

Abstract: A semiconductor device includes a first bit line disposed over a semiconductor substrate. The semiconductor device also includes a capacitor contact and a dielectric structure disposed over the semiconductor substrate and adjacent to the first bit line. The capacitor contact, the dielectric structure and the first bit line are separated from one another by an air gap structure.

Abstract: A semiconductor device includes a first bit line disposed over a semiconductor substrate. The semiconductor device also includes a capacitor contact and a dielectric structure disposed over the semiconductor substrate and adjacent to the first bit line. The capacitor contact, the dielectric structure and the first bit line are separated from one another by an air gap structure.

Abstract: A semiconductor structure includes a base layer with a top surface and a plurality of processed areas. A primary pattern is disposed on the top surface of the base layer, wherein the primary pattern has a pattern top surface, a processed area on the pattern top surface, and a sidewall, and the primary pattern has a first critical dimension, and the processed areas are on the part of the top surface of the base layer exposed by the primary pattern. A secondary pattern is disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension.

Abstract: The present disclosure provides a method for preparing a conductive plug. The method includes forming a first conductive structure over a substrate; forming a first dielectric structure over the first conductive structure; transforming a sidewall portion of the first conductive structure into a first dielectric portion; and removing the first dielectric portion such that a width of the first dielectric structure is greater than a width of a remaining portion of the first conductive structure.