Abstract: A first and second semiconductor device are bonded together using a bonding contact pad embedded within a bonding dielectric layer of the first semiconductor device and at least one bonding via embedded within a bonding dielectric layer of the second semiconductor device. The bonding contact pad extends a first dimension in a first direction perpendicular to the major surface of the first semiconductor device and a second dimension in a second direction parallel to the plane of the first semiconductor wafer, the second dimension being at least twice the first dimension. The bonding via extends a third dimension in the first direction and a fourth dimension in the second direction, the third dimension being at least twice the first dimension. The bonding contact pad and bonding via may be at least partially embedded in respective bonding dielectric layers in respective topmost dielectric layers of respective stacked interconnect layers.

Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

Abstract: A device includes first and second gate structures respectively extending across the first and second fins, and a gate isolation plug between a longitudinal end of the first gate structure and a longitudinal end of the second gate structure. The gate isolation plug comprises a first dielectric layer and a second dielectric layer over the first dielectric layer. The first dielectric layer has an upper portion and a lower portion below the upper portion. The upper portion has a thickness smaller than a thickness of the lower portion of the first dielectric layer.

Abstract: The present invention provides Wnt pathway agonists and related compositions, which may be used in any of a variety of therapeutic methods for the treatment of diseases.

Abstract: A battery charging and swapping system includes a plurality of charging seats, a first charging station, a first charging rail and a first conveying unit. The charging seats are operable to enter a first conveying space defined by the first charging station so as to be stored. The first charging rail is disposed at the first charging station, and supplies electrical energy to the charging seats. Via the first conveying unit, when one of the charging seats entering the first conveying space is carried and moved by the first conveying unit, at least one of the rest of the charging seats in the first conveying space is pushed by the one of the charging seats to move along the first conveying space.

Abstract: A package structure includes a bonding substrate, an integrated circuit, and a heat sink metal. The integrated circuit includes an active region facing the bonding substrate. The heat sink metal is located between the bonding substrate and the active region of the integrated circuit. The heat sink metal is electrically insulated with the integrated circuit.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may determine, via a first subscription of the UE, a trigger event for a conditional handover of the UE from a source network entity to a target network entity. The UE may determine, based at least in part on the trigger event, that a target band associated with the target network entity is not compatible with a serving band associated with a second subscription of the UE. The UE may store the trigger event for the conditional handover in a buffer of the UE. The UE may perform an action related to the conditional handover based at least in part on a condition being satisfied. Numerous other aspects are described.

Abstract: An information handling system includes a display panel having an active area that generates visual images and an inactive area disposed outside the active area. The inactive area having an alignment mark that is invisible to a naked eye.

Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.

Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.

Abstract: An optical member driving mechanism is provided. The optical member driving mechanism includes a first portion and a matrix structure. The first portion is connected to a first optical member and corresponds to a first light. The matrix structure is disposed on the first portion and corresponds to a second light, wherein the first light is different from the second light. The matrix structure includes a regularly-arranged structure.

Abstract: Disclosed is a system comprising a memory device and a processing device, operatively coupled with the memory device, to perform operations including identifying a group of memory cells corresponding to a first range of logical block addresses (LBAs). The operations performed by the processing device further include receiving a memory access command with respect to the group of memory cells. The operations performed by the processing device further include responsive to determining that a data structure associated with the group of memory cells references a second range of LBAs, blocking the memory access command; responsive to determining that the first range of LBAs does not include each LBA of the second range of LBAs, performing, on the group of memory cells, a trim operation; and responsive to determining that the data structure indicates the completion of the trim operation, performing a memory access operation specified by the memory access command.

Abstract: Gas detection devices comprise a dehydration unit a concentration unit, and a temperature control unit for controlling a temperature. The gas detection device includes a sampling mode in which sample gas flows into and out of the dehydration unit through a first port and a second port, respectively, wherein the volatile organic compounds in the sample gas are concentrated in the concentration unit. The temperature control unit may be configured such that the temperature of the sample gas after flowing out from the dehydration unit and before flowing into the concentration unit is not greater than a first preset temperature. Generation of condensed substances in the sample gas can be effectively avoided in a simple manner after the sample gas flows into the concentration unit, thereby further preventing ice blockage. Methods for detecting volatile organic compounds in a sample gas are also disclosed.

Abstract: A light emitting module includes a carrier, a light emitting element, a reflection layer, and a fluorescent layer. The light emitting element is disposed on the carrier. The reflection layer is disposed on the carrier and surrounds the light emitting element. The fluorescent layer covers at least part of the light emitting element. The disadvantages of over broad light emitting angle and low illuminance may be solved. Comparing with the related art, the present disclosure achieves an object of increasing the illuminance by at least 10%.

Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.

Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

Abstract: A switch module with an automatic switching function and a method for automatically switching the switch module according to the load, wherein a first comparator and a second comparator are configured to automatically determine whether the load is light or heavy according to the voltage divided by a first resistor and a second resistor and the voltage of a source resistor, thereby generating a voltage control signal. A plurality of transistors are configured to receive a gate input signal according to the voltage control signal, thereby selectively bringing a GaN transistor or a MOSFET transistor in a conducting state. In this way, the output quality and efficiency of the power supply at light and heavy loads can be improved according to the characteristics of different transistors.

Abstract: A logic cell structure includes a first portion, a second portion and a third portion. The first portion, arranged to be a first layout of a first semiconductor element, is placed in a first cell row of a substrate area extending in a first direction. The second portion, arranged to be a second layout of a second semiconductor element, is placed in a second cell row of the substrate area. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. The first, second and third portions are bounded by a bounding box with a height in a second direction and a width in the first direction. Respective centers of the first portion and the second portion are arranged in a third direction different from each of the first direction and the second direction.

Abstract: A substrate assembly is provided, including a first substrate, an active element layer, a plurality of first electrodes, a circuit substrate, and a plurality of second electrodes. The active element layer is disposed on the first substrate. The plurality of first electrodes are disposed on the first substrate and arranged along a first direction. The circuit substrate is partially overlapping the first substrate in a vertical projection direction. The plurality of second electrodes are disposed on the circuit substrate. A distance between the edge of one of the plurality of second electrodes and the edge of one of the plurality of first electrodes is greater than zero in the first direction, and a width of the one of the plurality of first electrodes is different from a width of the one of the plurality of second electrodes.

Abstract: Disclosed are near-eye displaying methods and systems capable of multiple depths of field imaging. The method comprises two steps. At a first step, one or more pixels of a self-emissive display emit a light to a collimator such that the light passing through the collimator is collimated to form a collimated light. At a second step, the self-emissive display provides at least one collimated light direction altering unit on a path of the light from the collimator to change direction of the collimated light to enable the collimated light from at least two pixels to intersect and focus at a different location so as to vary a depth of field.