Abstract: Methods, apparatuses, and systems related to a sense line and cell contact for a semiconductor structure are described. An example apparatus includes a first source/drain region and a second source/drain region, where the first source/drain region and the second source/drain region are separated by a channel, a gate opposing the channel, a sense line material coupled to the first source/drain region by a cell contact, where the cell contact is made from a combination of a first polysilicon material and a second polysilicon material, and a storage node coupled to the second source/drain region.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.

Abstract: A detection method is provided to identify the communication protocol being used between a serial communication interface and an external device. The protocols include URAT, I2C bus, and SPI. The serial communication interface includes a first pin and a second pin. The first pin is shared by the transmission line of UART, the serial clock line of I2C, and the slave-select line of SPI. The second pin is shared by the receive line of UART, the serial data line of I2C, and the clock line of SPI. The detection method includes determining whether the communication protocol is UART, I2C, or SPI based on the signal edges of the first pin and the second pin.

Abstract: Provided is a hydrophilic phosphorus ligand with the structure of formula 1. X is Y is m is an integer from 1 to 20, A independently is *—O(CH2)n—, n is an integer from 1 to 5, *- is a bond close to triphenylphosphine, and - is a bond away from triphenylphosphine.

Abstract: Provided are an organometallic complex coating solution and a near-infrared absorption film, including an organometallic complex, a phosphorus-containing dispersant, and optical resin. The present disclosure greatly reduces the temperature and time of the film-forming process by formulating components of the organometallic complex coating solution.

Abstract: A flexible circuit board includes liquid crystal polymer (LCP) layers and metal layers including circuit routes. Each of the LCP layers includes via structures. The metal layers and the LCP layers are alternatively stacked to form a multi-layer structure. Adjacent metal layers are electrically connected through the via structures. Some via structures of different LCP layers are substantially aligned with one another to form a stack of via structures. Each of the via structures includes openings filled with conductive material. The size of the opening fulfils the following equation: Vb?cos(Bh/Vh)*Vt/k*2, where Vb is a diameter of a smaller aperture, Vt is a diameter of a bigger aperture, Vh is a combined thickness of a LCP layer and a metal layer, Bh is a thickness of a LCP layer and k is a tensile modulus.

Abstract: A computer system for failing a secure boot in a case tampering event comprises a microcontroller unit (MCU); a trusted platform module (TPM), for generating random bytes for a secure boot of the computer system; a bootloader, for storing information comprising the random bytes in the MCU and at least one hardware of the computer system and performing the secure boot, wherein the TPM is comprised in the bootloader; an operating system (OS), for performing the secure boot; and at least one sensor, coupled to the MCU, for detecting a case tampering event, and transmitting a signal for triggering a deletion of the random bytes, if the case tampering event happens. The MCU performs the operation of deleting the random bytes stored in the MCU and the at least one hardware according to a power supply, in response to the signal.

Abstract: A computer system for failing a secure boot in a case tampering event comprises a trusted platform module (TPM), for generating a plurality of random bytes for a secure boot of the computer system; a bootloader, for storing information in at least one hardware of the computer system and performing the secure boot, wherein the information comprises the plurality of random bytes, and the TPM is comprised in the bootloader; an operating system (OS), for performing the secure boot; and at least one sensor, for detecting a case tampering event in the computer system, and transmitting a signal for triggering a deletion of the plurality of random bytes, if the case tampering event happens in the computer system. The bootloader or the OS performs the operation of deleting the plurality of random bytes stored in the at least one hardware to fail the secure boot, in response to the signal.

Abstract: An electronic device for signaling a first communication target and a second communication target includes a processor, an input unit and a timer. The input unit is coupled to the processor, and causes the processor to obtain an input data. The timer is coupled to the processor, and is controlled by the processor to cause the processor to receive an interrupt request signal. The processor obtains a first electronic data and a second electronic data being different from the first electronic data based on the input data in response to the interrupt request signal, causes the first electronic data to be sent toward the first communication target based on a first specific application communication protocol, and causes the second electronic data to be sent toward the second communication target based on a second specific application communication protocol being different from the first specific application communication protocol.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.

Abstract: A circuit with a metal-oxide semiconductor field-effect transistor and a diode module is applied to a power factor correction circuit, which can effectively reduce the heat generated by the whole system under heavy load. The circuit includes a metal-oxide semiconductor field-effect transistor and a diode module and a load determination unit. The diode module includes a plurality of diodes with a switch. The load determination unit can control the connection/disconnection of each diode in the diode module based on the magnitude of the load current. It can effectively reduce the current generated by each diode due to the load, thereby reducing the heat generation of the overall system. Moreover, due to the contact capacitance effect after the diodes are connected in parallel, the electromagnetic interference (EMI) characteristics of the power factor correction circuit of the system can be further optimized.

Abstract: An electromagnetic interference regulator by use of capacitive parameters of the field-effect transistor for detecting the induced voltage and the induced current of the field-effect transistor to determine whether the operating frequency of the field-effect transistor is within the preset special management frequency of electromagnetic interference. When the basic frequency and the multiplied frequency exceed the limit, the content of the external capacitor unit can be adjusted to assist the products using field-effect transistors to maintain excellent electromagnetic interference adjustment capabilities under various loads, thereby optimizing the characteristics of electromagnetic interference.

Abstract: A control device for controlling a first variable physical parameter characterized based on a physical parameter application state includes a sensing unit and a processing unit. The sensing unit sensing a second variable physical parameter to generate a sense signal, wherein the second variable physical parameter is characterized based on a physical parameter application range represented by a measurement value application range. The processing unit is coupled to the sensing unit, obtains a measured value in response to the sense signal, and causes the first variable physical parameter to be in the physical parameter application state under a condition that the physical parameter application range which the second variable physical parameter is currently in is determined by checking a mathematical relation between the measured value and the measurement value application range.

Abstract: A metal-oxide semiconductor field-effect transistor with asymmetric parallel die and an implementation method thereof, comprising an inductor, a load recognition control unit and a metal-oxide semiconductor field-effect transistor having a first die, a second die, and a switch. The first die is larger in size than the second die. The inductor can produce a voltage signal when the load changes. The switch is controlled by the load recognition control unit such that different dies are switched on under different load conditions, thereby improving efficiency under light load condition in addition to reducing volume and cost.

Abstract: A circuit with a metal-oxide semiconductor field-effect transistor and a diode module is applied to a power factor correction circuit, which can effectively reduce the heat generated by the whole system under heavy load, The circuit includes a metal-oxide semiconductor field-effect transistor and a diode module and a load determination unit. The diode module includes a plurality of diodes with a switch. The load determination unit can control the connection/disconnection of each diode in the diode module based on the magnitude of the load current. It can effectively reduce the current generated by each diode due to the load, thereby reducing the heat generation of the overall system. Moreover, due to the contact capacitance effect after the diodes are connected in parallel, the electromagnetic interference (EMI) characteristics of the power factor correction circuit of the system can be further optimized.

Abstract: A hybrid metal-oxide semiconductor field-effect transistor with variable gate impedance and an implementation method thereof, wherein the hybrid metal-oxide semiconductor field-effect transistor has the characteristic of changing the on-resistance according to different drive voltages. By use of a feedback loop and a variable gate drive voltage generator which can vary the generated gate drive voltage based on different loads, the present disclosure can still adjust the gate drive voltage under different load conditions without requiring a plurality of metal-oxide semiconductor field-effect transistors in series/parallel to achieve the lowest power loss.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.

Abstract: graphite composite laminated heat-dissipating structure and a manufacturing method thereof are disclosed. The structure includes a metal substrate and a graphite heat-dissipating layer. The metal substrate has a first surface having a roughness ranging between 0.01 and 10 ?m. The graphite heat-dissipating layer is composed of pure graphite and is directly formed on the first surface by means of physical vapor deposition using a carbon sputtering target. The graphite heat-dissipating layer has a thickness ranging between 0.05 and 2 ?m. The manufacturing method includes S1: directly forming a graphite heat-dissipating layer on a first surface of a metal substrate by means of physical vapor deposition using a carbon sputtering target after the metal substrate has received plasma treatment or infrared heating; and S2: stopping the physical vapor deposition when the graphite heat-dissipating layer has a thickness ranging between 0.05 and 2 ?m.

Abstract: An electronic device includes a storage unit, an input unit and a processing unit. The input unit sequentially receives a first user input operation, a second user input operation and a third user input operation. The processing unit causes the storage unit to prepare a first electronic data in response to the first user input operation, causes a second electronic data derived from the first electronic data to be formed in the storage unit in response to the second user input operation, sends the first electronic data toward a first communication target based on a first specific application communication protocol in response to the third user input operation, and sends the second electronic data toward a second communication target based on a second specific application communication protocol being different from the first specific application communication protocol in response to the third user input operation.

Abstract: A method of blind spot detection is provided. The method of blind spot detection is used for a vehicle including a first vehicle body and a second vehicle body dragged by the first vehicle body. The method of blind spot detection comprises the following steps: obtaining a turning angle information of the second vehicle body relative to the first vehicle body by a first sensor while the vehicle is moving; determining a predetermined information related to the vehicle and/or a second sensor; dynamically defining a blind spot area around the vehicle according to the turning angle information and the predetermined information; and receiving a sensing signal regarding an object around the vehicle from the second sensor to determine whether the object is located in the blind spot area.