Patents by Inventor Kuo-In Chen

Kuo-In Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070262360
    Abstract: High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, or equivalents, and the current flow is in the [110] direction, or equivalents, when a negative potential is applied to the gate with respect to the source. The enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total “on” resistance of the device.
    Type: Application
    Filed: December 22, 2006
    Publication date: November 15, 2007
    Inventors: Deva Pattanayak, Kuo-In Chen, The-Tu Chau
  • Publication number: 20070221989
    Abstract: Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorous. The novel red Phosphorous doped substrate enables a desirable low drain-source resistance.
    Type: Application
    Filed: March 21, 2006
    Publication date: September 27, 2007
    Inventors: The-Tu Chau, Sharon Shi, Qufei Chen, Martin Hernandez, Deva Pattarayak, Kyle Terrill, Kuo-In Chen
  • Publication number: 20070187753
    Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.
    Type: Application
    Filed: January 26, 2007
    Publication date: August 16, 2007
    Applicant: Siliconix incorporated
    Inventors: Deva Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Lui, Kuo-In Chen, Sharon Shi
  • Publication number: 20070048966
    Abstract: Systems and methods for narrow semiconductor trench structures. In a first method embodiment, a method for forming a narrow trench comprises forming a first layer of insulating material on a substrate and creating a trench through the first layer of insulating material and into the substrate. A second insulating material is formed on the first layer and on exposed portions of the trench and the second insulating material is removed from the first layer of insulating material and the bottom of the trench. The trench is filled with an epitaxial material and the first layer of insulating material is removed. A narrow trench is formed by the removal of remaining portions of the second insulating material.
    Type: Application
    Filed: March 9, 2006
    Publication date: March 1, 2007
    Inventors: The-Tu Chau, Hoang Le, Kuo-In Chen
  • Patent number: 7183610
    Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: February 27, 2007
    Assignee: Siliconix incorporated
    Inventors: Deva N. Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Hong Lui, Kuo-In Chen, Sharon Shi
  • Publication number: 20050242392
    Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.
    Type: Application
    Filed: April 30, 2004
    Publication date: November 3, 2005
    Applicant: Siliconix incorporated
    Inventors: Deva Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Lui, Kuo-In Chen, Sharon Shi
  • Patent number: 6921697
    Abstract: Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the substrate along the trench bottom. The thick insulative layer separates the trench gate from the drain region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications. In an exemplary fabrication process embodiment, the thick insulative layer is deposited on the bottom of the trench. A thin insulative gate dielectric is formed on the exposed sidewall and is coupled to the thick insulative layer. A gate is formed in the remaining trench volume. The process is completed with body and source implants, passivation, and metallization.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: July 26, 2005
    Assignee: Siliconix Incorporated
    Inventors: Mohamed N. Darwish, Frederick P. Giles, Kam Hong Lui, Kuo-In Chen, Kyle Terrill
  • Patent number: 6903412
    Abstract: The gate oxide layer of a trench MIS device includes a graduated transition region, where the thickness of the gate oxide layer decreases gradually from a thick section adjacent the bottom of the trench to a thin section adjacent the sidewall of the trench. The PN junction between the body and drain regions intersects the trench in the transition region. This structure allows for a greater margin of error in the placement of the PN junction during the manufacture of the device, since the intersection between the PN junction can be located anywhere in the transition region. The MIS device also has improved breakdown characteristics.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: June 7, 2005
    Assignee: Siliconix incorporated
    Inventors: Mohamed N. Darwish, Christiana Yue, Frederick P. Giles, Kam Hong Lui, Kuo-In Chen, Kyle Terrill, Deva N. Pattanayak
  • Patent number: 6882000
    Abstract: Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the substrate along the trench bottom. The thick insulative layer separates the trench gate from the drain region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications. In an exemplary fabrication process embodiment, the thick insulative layer is deposited on the bottom of the trench. A thin insulative gate dielectric is formed on the exposed sidewall and is coupled to the thick insulative layer. A gate is formed in the remaining trench volume. The process is completed with body and source implants, passivation, and metallization.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: April 19, 2005
    Assignee: Siliconix Incorporated
    Inventors: Mohamed N. Darwish, Frederick P. Giles, Kam Hong Lui, Kuo-In Chen, Kyle Terrill
  • Patent number: 6875657
    Abstract: A process for manufacturing a trench MIS device includes depositing a conformal nitride layer in the trench; etching the nitride layer to create an exposed area at the bottom of the trench; and heating the substrate and thereby growing an oxide layer in the exposed area. This process causes the mask layer to “lift off”, creating a “bird's beak” structure. This becomes a “transition region”, where the thickness of the oxide layer decreases gradually in a direction away from the exposed area. The method further includes diffusing a dopant into the substrate, the dopant forming a PN junction with a remaining portion of said substrate, and controlling the diffusion such that the PN junction intersects the trench in the transition region. Because the thickness of the oxide layer decreases gradually, the PN junction does not need to be located at a particular point, i.e., there is a margin of error. This improves the manufacturability of the device and enhances its breakdown characteristics.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: April 5, 2005
    Assignee: Siliconix incorporated
    Inventors: Christiana Yue, Mohamed N. Darwish, Frederick P. Giles, Kam Hong Lui, Kuo-In Chen, Kyle Terrill, Deva N. Pattanayak
  • Patent number: 6849898
    Abstract: Trench MOSFETs including active corner regions and a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such MOSFETs. In an exemplary embodiment, the trench MOSFET includes a thick insulative layer centrally located at the bottom of the trench. A thin gate insulative layer lines the sidewall and a peripheral portion of the bottom surface of the trench. A gate fills the trench, adjacent to the gate insulative layer. The gate is adjacent to the sides and top of the thick insulative layer. The thick insulative layer separates the gate from the drain conductive region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: February 1, 2005
    Assignee: Siliconix incorporated
    Inventors: Mohamed N. Darwish, Frederick P. Giles, Kam Hong Lui, Kuo-In Chen, Kyle Terrill
  • Publication number: 20030062570
    Abstract: Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the substrate along the trench bottom. The thick insulative layer separates the trench gate from the drain region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications. In an exemplary fabrication process embodiment, the thick insulative layer is deposited on the bottom of the trench. A thin insulative gate dielectric is formed on the exposed sidewall and is coupled to the thick insulative layer. A gate is formed in the remaining trench volume. The process is completed with body and source implants, passivation, and metallization.
    Type: Application
    Filed: October 3, 2002
    Publication date: April 3, 2003
    Inventors: Mohamed N. Darwish, Frederick P. Giles, Kam Hong Lui, Kuo-In Chen, Kyle Terrill
  • Publication number: 20030030092
    Abstract: Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the substrate along the trench bottom. The thick insulative layer separates the trench gate from the drain region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications. In an exemplary fabrication process embodiment, the thick insulative layer is deposited on the bottom of the trench. A thin insulative gate dielectric is formed on the exposed sidewall and is coupled to the thick insulative layer. A gate is formed in the remaining trench volume. The process is completed with body and source implants, passivation, and metallization.
    Type: Application
    Filed: August 10, 2001
    Publication date: February 13, 2003
    Inventors: Mohamed N. Darwish, Frederick P. Giles, Kam Hong Lui, Kuo-In Chen, Kyle Terrill
  • Publication number: 20030032247
    Abstract: Trench MOSFETs including active corner regions and a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such MOSFETs. In an exemplary embodiment, the trench MOSFET includes a thick insulative layer centrally located at the bottom of the trench. A thin gate insulative layer lines the sidewall and a peripheral portion of the bottom surface of the trench. A gate fills the trench, adjacent to the gate insulative layer. The gate is adjacent to the sides and top of the thick insulative layer. The thick insulative layer separates the gate from the drain conductive region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications.
    Type: Application
    Filed: August 10, 2001
    Publication date: February 13, 2003
    Applicant: Siliconix inorporated
    Inventors: Mohamed N. Darwish, Frederick P. Giles, Kam Hong Lui, Kuo-In Chen, Kyle Terrill
  • Publication number: 20030030104
    Abstract: The gate oxide layer of a trench MIS device includes a graduated transition region, where the thickness of the gate oxide layer decreases gradually from a thick section adjacent the bottom of the trench to a thin section adjacent the sidewall of the trench. The PN junction between the body and drain regions intersects the trench in the transition region. This structure allows for a greater margin of error in the placement of the PN junction during the manufacture of the device, since the intersection between the PN junction can be located anywhere in the transition region. The MIS device also has improved breakdown characteristics.
    Type: Application
    Filed: March 26, 2002
    Publication date: February 13, 2003
    Inventors: Mohamed N. Darwish, Christiana Yue, Frederick P. Giles, Kam Hong Lui, Kuo-In Chen, Kyle Terrill, Deva N. Pattanayak
  • Publication number: 20030032248
    Abstract: A process for manufacturing a trench MIS device includes depositing a conformal nitride layer in the trench; etching the nitride layer to create an exposed area at the bottom of the trench; and heating the substrate and thereby growing an oxide layer in the exposed area. This process causes the mask layer to “lift off”, creating a “bird's beak” structure. This becomes a “transition region”, where the thickness of the oxide layer decreases gradually in a direction away from the exposed area. The method further includes diffusing a dopant into the substrate, the dopant forming a PN junction with a remaining portion of said substrate, and controlling the diffusion such that the PN junction intersects the trench in the transition region. Because the thickness of the oxide layer decreases gradually, the PN junction does not need to be located at a particular point, i.e., there is a margin of error.
    Type: Application
    Filed: March 26, 2002
    Publication date: February 13, 2003
    Inventors: Christiana Yue, Mohamed N. Darwish, Frederick P. Giles, Kam Hong Lui, Kuo-In Chen, Kyle Terrill, Deva N. Pattanayak
  • Patent number: 5689128
    Abstract: The cell density of a trenched DMOS transistor is increased by overcoming the problem of lateral diffusion of deep P+body regions. This problem is solved in three versions. In a first version, the deep P+body region is formed using a high energy implant into a single epitaxial layer. In a second version, a double epitaxial layer is used with a somewhat lower but still high energy deep P+body implant. In a third version, there is no deep P+body implant but only the double epitaxial layer is used. The cell density is improved to more than 12 million cells per square inch in each of the three versions.
    Type: Grant
    Filed: August 21, 1995
    Date of Patent: November 18, 1997
    Assignee: Siliconix incorporated
    Inventors: Fwu-Iuan Hshieh, Mike F. Chang, Kuo-In Chen, Richard K. Williams, Mohamed Darwish