Patents by Inventor Kuo Pin Chang

Kuo Pin Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10886222
    Abstract: Disclosed herein is a method of forming a semiconductor structure. The method includes the steps of: forming a first dielectric layer having a first through hole on a precursor substrate, in which the first through hole passes through the first dielectric layer; filling a sacrificial material in the first through hole; forming a second dielectric layer having a second through hole over the first dielectric layer, in which the second through hole exposes the sacrificial material in the first through hole, and the second through hole has a bottom width less than a top width of the first through hole; removing the sacrificial material after forming the second dielectric layer having the second through hole; forming a barrier layer lining sidewalls of the first and second through holes; and forming a conductive material in the first and second through holes.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: January 5, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Wei Jiang, Kuo-Pin Chang, Chih-Wei Hu
  • Patent number: 10878915
    Abstract: A method for programming a memory device is provided. The memory device includes first to fourth memory cells, in which the first and second memory cells share a first erase gate, and the third and fourth memory cells share a second erase gate. The method includes applying a first voltage to control gates of the first and third memory cell; applying a second voltage to control gates of the second and fourth memory cells, in which the first voltage is higher than the second voltage; applying a third voltage to a select gate of the first memory cell; and applying a fourth voltage to select gates of the second to fourth memory cell, in which the third voltage is higher than the fourth voltage.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Pin Chang, Hsien-Jung Chen, Chien-Hung Liu, Chih-Wei Hung
  • Patent number: 10816399
    Abstract: The transmissive sampling module includes a light emitting element, an accommodation tank, and a lens group having a positive refractive power. The light emitting element is configured to emit an illumination beam. The accommodation tank is configured to accommodate an object to be measured. The lens group includes a first lens and a second lens. The first lens and the second lens are respectively located at a first side and a second side of the accommodation tank. The accommodation tank is located between the first lens and the second lens. The illumination beam is transmitted to the object after passing through the first lens. The object converts the illumination beam into a sample beam. The sample beam is transmitted to a main body of the spectrometer after passing through the second lens. A transmissive spectrometer having a transmissive sampling module is also provided.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: October 27, 2020
    Assignee: InnoSpectra Corporation
    Inventors: Kuo-Sheng Huang, Fei-Peng Chang, Hsi-Pin Li
  • Publication number: 20200335510
    Abstract: A semiconductor structure includes a substrate, conductive layers, dielectric layers, an isolation structure, a first memory structure, and a second memory structure. The conductive layers and the dielectric layers are interlaced and stacked on the substrate. The isolation structure is disposed on the substrate and through the conductive layers and the dielectric layers. Each of the first and second memory structures has a radius of curvature. The first and second memory structures penetrate through the conductive layers and the dielectric layers and are disposed on opposite sidewalls of the isolation structure. Each of the first and second memory structures includes protecting structures and a memory structure layer including a memory storage layer. The protecting structures are disposed at two ends of the memory storage layer, and an etching selectivity to the protecting structures is different from an etching selectivity to the memory storage layer.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 22, 2020
    Inventors: Yu-Wei JIANG, Kuo-Pin CHANG, Chieh-Fang CHEN
  • Patent number: 10811427
    Abstract: A semiconductor structure includes a substrate, conductive layers, dielectric layers, an isolation structure, a first memory structure, and a second memory structure. The conductive layers and the dielectric layers are interlaced and stacked on the substrate. The isolation structure is disposed on the substrate and through the conductive layers and the dielectric layers. Each of the first and second memory structures has a radius of curvature. The first and second memory structures penetrate through the conductive layers and the dielectric layers and are disposed on opposite sidewalls of the isolation structure. Each of the first and second memory structures includes protecting structures and a memory structure layer including a memory storage layer. The protecting structures are disposed at two ends of the memory storage layer, and an etching selectivity to the protecting structures is different from an etching selectivity to the memory storage layer.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: October 20, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Wei Jiang, Kuo-Pin Chang, Chieh-Fang Chen
  • Publication number: 20200328154
    Abstract: Disclosed herein is a method of forming a semiconductor structure. The method includes the steps of: forming a first dielectric layer having a first through hole on a precursor substrate, in which the first through hole passes through the first dielectric layer; filling a sacrificial material in the first through hole; forming a second dielectric layer having a second through hole over the first dielectric layer, in which the second through hole exposes the sacrificial material in the first through hole, and the second through hole has a bottom width less than a top width of the first through hole; removing the sacrificial material after forming the second dielectric layer having the second through hole; forming a barrier layer lining sidewalls of the first and second through holes; and forming a conductive material in the first and second through holes.
    Type: Application
    Filed: April 10, 2019
    Publication date: October 15, 2020
    Inventors: Yu-Wei JIANG, Kuo-Pin CHANG, Chih-Wei HU
  • Publication number: 20200309596
    Abstract: A transmissive sampling module used to fix a test object to allow a spectrometer body to obtain optical information of the test object and includes a bearing base, a light emitting element, an adapter element and a sample accommodating device. The bearing base includes a first accommodating tank body. The light emitting element is disposed in the bearing base and used to emit an illumination beam. The adapter element is disposed in the first accommodating tank body and further includes a body portion and an abutting rib extending from the body portion. The body portion and the abutting rib jointly form a second accommodating tank body. The sample accommodating device at least partially surface-contacts with a second tank surface through a second light exit. A spectrometer having the transmissive sampling module is provided.
    Type: Application
    Filed: March 25, 2020
    Publication date: October 1, 2020
    Applicant: InnoSpectra Corporation
    Inventors: Fei-Peng Chang, Hsi-Pin Li, Kuo-Sheng Huang
  • Publication number: 20200185440
    Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.
    Type: Application
    Filed: February 13, 2020
    Publication date: June 11, 2020
    Inventors: Chia-Yu WEI, Fu-Cheng CHANG, Hsin-Chi CHEN, Ching-Hung KAO, Chia-Pin CHENG, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
  • Patent number: 10593697
    Abstract: A memory device includes a channel element, a gate electrode layer and a memory element. The channel element has a U shape. The gate electrode layer is electrically coupled to the channel element. The memory element surrounds a sidewall channel surface of the channel element.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 17, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Wei Hu, Teng-Hao Yeh, Yu-Wei Jiang, Kuo-Pin Chang
  • Patent number: 10566361
    Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: February 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yu Wei, Fu-Cheng Chang, Hsin-Chi Chen, Ching-Hung Kao, Chia-Pin Cheng, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
  • Publication number: 20190393445
    Abstract: A light emitting device including a base, a first electrode, a barrier structure layer, a light emitting layer and a second electrode is provided. The barrier structure layer includes a first barrier layer in contact with the first electrode, a second barrier layer and a third barrier layer. The first barrier layer, the second barrier layer and the third barrier layer stack sequentially. The materials of the first barrier layer and the third barrier layer include a dielectric material. The material of the second barrier layer includes a metal material. A boundary between the third barrier layer and the second barrier layer keeps a vertical distance from the first electrode. The light emitting structure layer is disposed between the first electrode and the second electrode and surrounded by the barrier structure layer. The thickness of the light emitting structure layer is not greater than the vertical distance.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 26, 2019
    Applicant: Au Optronics Corporation
    Inventors: Kent-Yi Lee, Wen-Pin Chen, Wen-Tai Chen, Kuo-Jui Chang, Tsu-Wei Chen, Kuo-Kuang Chen, Shih-Hsing Hung
  • Publication number: 20190301929
    Abstract: The transmissive sampling module includes a light emitting element, an accommodation tank, and a lens group having a positive refractive power. The light emitting element is configured to emit an illumination beam. The accommodation tank is configured to accommodate an object to be measured. The lens group includes a first lens and a second lens. The first lens and the second lens are respectively located at a first side and a second side of the accommodation tank. The accommodation tank is located between the first lens and the second lens. The illumination beam is transmitted to the object after passing through the first lens. The object converts the illumination beam into a sample beam. The sample beam is transmitted to a main body of the spectrometer after passing through the second lens. A transmissive spectrometer having a transmissive sampling module is also provided.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 3, 2019
    Applicant: InnoSpectra Corporation
    Inventors: Kuo-Sheng Huang, Fei-Peng Chang, Hsi-Pin Li
  • Publication number: 20190115313
    Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including an IMD layer disposed over the first substrate and a plurality of conductive bumps disposed in the IMD layer; receiving a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the IMD layer is exposed through the patterned adhesive; and bonding the first substrate with the second substrate, wherein a top surface of the at least portion of the IMD layer is exposed through the patterned adhesive after bonding the first substrate with the second substrate.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 18, 2019
    Inventors: ALEXANDER KALNITSKY, YI-YANG LEI, HSI-CHING WANG, CHENG-YU KUO, TSUNG LUNG HUANG, CHING-HUA HSIEH, CHUNG-SHI LIU, CHEN-HUA YU, CHIN-YU KU, DE-DUI LIAO, KUO-CHIO LIU, KAI-DI WU, KUO-PIN CHANG, SHENG-PIN YANG, ISAAC HUANG
  • Patent number: 10163849
    Abstract: A method of manufacturing a semiconductor structure, including receiving a first substrate including a plurality of conductive bumps disposed over the first substrate; receiving a second substrate; disposing an adhesive over the first substrate; removing a portion of the adhesive to expose at least one of the plurality of conductive bumps; and bonding the first substrate with the second substrate.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Alexander Kalnitsky, Yi-Yang Lei, Hsi-Ching Wang, Cheng-Yu Kuo, Tsung Lung Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu, Chin-Yu Ku, De-Dui Liao, Kuo-Chio Liu, Kai-Di Wu, Kuo-Pin Chang, Sheng-Pin Yang, Isaac Huang
  • Publication number: 20180047701
    Abstract: A method of manufacturing a semiconductor structure, including receiving a first substrate including a plurality of conductive bumps disposed over the first substrate; receiving a second substrate; disposing an adhesive over the first substrate; removing a portion of the adhesive to expose at least one of the plurality of conductive bumps; and bonding the first substrate with the second substrate.
    Type: Application
    Filed: October 23, 2017
    Publication date: February 15, 2018
    Inventors: ALEXANDER KALNITSKY, YI-YANG LEI, HSI-CHING WANG, CHENG-YU KUO, TSUNG LUNG HUANG, CHING-HUA HSIEH, CHUNG-SHI LIU, CHEN-HUA YU, CHIN-YU KU, DE-DUI LIAO, KUO-CHIO LIU, KAI-DI WU, KUO-PIN CHANG, SHENG-PIN YANG, ISAAC HUANG
  • Patent number: 9799625
    Abstract: A method of manufacturing a semiconductor structure, comprising: receiving a first substrate including a first surface, a second surface opposite to the first surface and a plurality of conductive bumps disposed over the first surface; receiving a second substrate; disposing an adhesive over the first substrate or the second substrate; heating the adhesive in a first ambiance; bonding the first substrate with the second substrate by applying a force of less than about 10,000N upon the first substrate or the second substrate and heating the adhesive in a second ambiance; and thinning down a thickness of the first substrate from the second surface.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: October 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Alexander Kalnitsky, Yi-Yang Lei, Hsi-Ching Wang, Cheng-Yu Kuo, Tsung Lung Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu, Chin-Yu Ku, De-Dui Liao, Kuo-Chio Liu, Kai-Di Wu, Kuo-Pin Chang, Sheng-Pin Yang, Isaac Huang
  • Patent number: 9761319
    Abstract: A reading method for preventing a read disturbance and a memory using the same are provided. The reading method includes the following steps: At least one of a plurality of string select lines is selected and a predetermined string select voltage is applied to the selected string select line. Only one of a plurality of ground select lines is selected and a predetermined ground select voltage is applied to the selected ground select line.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: September 12, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuo-Pin Chang, Teng-Hao Yeh, Hang-Ting Lue
  • Patent number: 9747989
    Abstract: A memory device and a control method of the memory device are provided. The memory device includes a decoding circuit, Q switching circuits and Q blocks. The decoding circuit generates Q select signals. A k-th select signal of the Q select signals has a first select voltage. The other (Q?1) select signals have a second select voltage. The Q switching circuits receive an erase voltage, and generate Q common source line signals according to the Q select signals. A k-th common source line signal of the Q common source line signals generated by a k-th switching circuit of the Q switching circuits has the erase voltage. The Q blocks receive the Q common source line signals, respectively. A k-th block of the Q blocks is erased according to the k-th common source line signal.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: August 29, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Kuo-Pin Chang
  • Patent number: 9721668
    Abstract: A memory device has a divided reference line structure which supports sub-block erase in NAND memory including a plurality of blocks. Each block in the plurality of blocks is coupled to a set of Y reference lines, where Y is two or more. Each block in the plurality of blocks includes a single reference select line (RSL), which is operable to connect each sub-block in the block to a corresponding reference line in the set of Y reference lines. A control circuit can be included on the device which is configured for an erase operation to erase a selected sub-block in a selected block.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: August 1, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Kuo-Pin Chang
  • Patent number: 9685233
    Abstract: A multiple bits per cell memory is operated by applying a one-pass, multiple-level programming, using a single pulse sequence one time (or in one-pass), such as an incremental pulse program sequence, with program verify steps for multiple target program levels, to program multiple bits per cell in a plurality of memory cells. Using these techniques, the number of program pulses required, and the time required for programming the data can be reduced. As a result, an improvement in programming throughput and a reduction in disturbance conditions are achieved. Variants of the one-pass, multiple-level programming operation can be adopted for a variety of memory cell types, memory architectures, programming speeds, and data storage densities.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: June 20, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Chang Hsieh, Ti-Wen Chen, Yung Chun Li, Kuo-Pin Chang