Abstract: One embodiment of the present disclosure provides an optical device which includes a waveguide and a light modulator. The light modulator includes a phase-change material and is in direct contact with an outer surface of the waveguide. The optical device also includes a thermal conducting member. The thermal conducting member is positioned on the light modulating member. The optical device further includes a heating member. The heating member is placed on the thermal conducting member and is distant away from the light modulator and the waveguide. The heat produced from the heating member is transferred to the light modulator through the thermal conducting member thereby inducing a phase transition of the light modulator.

Abstract: Phase change material (PCM) switches and methods of fabrication thereof that provide improved thermal confinement within a phase change material layer. A PCM switch may include a dielectric capping layer between a heater pad and the phase change material layer of the PCM switch that is laterally-confined such opposing sides of the dielectric capping layer the heater pad may form continuous surfaces extending transverse to the signal transmission pathway across the PCM switch. Heat transfer from the heater pad through the dielectric capping layer to the phase change material layer may be predominantly vertical, with minimal thermal dissipation along a lateral direction. The localized heating of the phase change material may improve the efficiency of the PCM switch enabling lower bias voltages, minimize the formation of regions of intermediate resistivity in the PCM switch, and improve the parasitic capacitance characteristics of the PCM switch.

Abstract: One embodiment of the present disclosure provides an optical device which includes a waveguide and a light modulator. The light modulator comprising a bridge segment positioned on the waveguide, wherein the bridge segment comprises a phase-change material. The optical device also includes a heating member. The heating member includes an intermediate segment and two electric contact segments. The intermediate segment is in direct contact with the bridge segment of the light modulator. The two electric contact segments are connected to two ends of the intermediate segment, wherein heat produced from the heating member is directly transferred to the bridge segment of the light modulator thereby inducing a phase transition thereof.

Abstract: A memory device is provided in various embodiments. The memory device, in those embodiments, has an ovonic threshold switching (OTS) selector comprising multiple layers of OTS materials to achieve a low leakage current and as well as relatively low threshold voltage for the OTS selector. The multiple layers can have at least one layer of low bandgap OTS material and at least one layer of high bandgap OTS material.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, and a heater element on the semiconductor substrate, the heater element configured to generate heat in response to a current flowing therethrough. The semiconductor device also includes a conductor material having a programmable conductivity, and an insulator layer between the heater element and the conductor material, where the conductor material is configured to be programmed by applying one or more voltage differences to one or more of the heater element and the conductor material, and where a capacitance between the conductor material and the heater element is configured to be controlled by the voltage differences such that the capacitance is lower while the conductor material is being programmed than while the conductor material is not being programmed.

Abstract: Structures and fabrication methods are disclosed wherein a switch and a capacitor are fabricated sharing the same process flow without the use of an extra mask. A first capacitor electrode is formed in parallel in the same metal layer using the same mask as a component of the PCM switch (e.g., a PCM switch heater electrode). A second capacitor electrode is formed in parallel in the same metal layer using the same mask as another component of the PCM switch (e.g., a PCM switch input pad or a PCM switch heat spreader). The capacitor insulator is formed in parallel in the same layer using the same mask as a PCM switch insulator (e.g., TBR or insulator between heat spreader and PCM layer).

Abstract: An embodiment phase change material switch may include a first phase change material element, a second phase change material element, a first conductor electrically connected to a first end of each of the first phase change material element and the second phase change material element such that the first conductor is configured as a first terminal of an electrical circuit having a parallel configuration, a second conductor electrically connected to a second end of each of the first phase change material element and the second phase change material element such that the second conductor is configured as a second terminal of the electrical circuit having the parallel configuration, and a heating device coupled to the first phase change material element and to the second phase change material element and configured to supply a heat pulse to the first phase change material element and to the second phase change material element.

Abstract: A device structure includes a first series connection of a first phase change memory (PCM) switch and a second PCM switch. The first PCM switch includes a first heater line, a first PCM line, and a first contact electrode and a second contact electrode located on the first heater line. The second PCM switch includes a second heater line, a second PCM line, and a third contact electrode and a fourth contact electrode located on the second heater line. The second contact electrode is electrically connected to the third contact electrode. The fourth contact electrode is electrically grounded. One of the first contact electrode and the second contact electrode includes an radio-frequency (RF) signal input port. Another of the first contact electrode and the second contact electrode comprises an RF signal output port. The device structure may function as a combination PCM switch that decreases noise level during signal transmission.

Abstract: A semiconductor device includes a semiconductor substrate having a first source/drain region, a semiconductor layer, a first floating gate electrode, a first control gate electrode, a second floating gate electrode, a second control gate electrode, and an erase gate electrode. The semiconductor layer extends upward from the first source/drain region of the semiconductor substrate. The first floating gate electrode laterally surrounds the first semiconductor layer. The first control gate electrode laterally surrounds the first floating gate electrode and the first semiconductor layer. The second floating gate electrode laterally surrounds the first semiconductor layer. The second control gate electrode laterally surrounds the second floating gate electrode and the semiconductor layer.

Abstract: A device structure includes a voltage regulator circuit, which includes: a first semiconductor die including a pulse width modulation (PWM) circuit and connected to a PWM voltage output node at which a pulsed voltage output is generated; and a series connection of an inductor and a parallel connection circuit, the parallel connection circuit including a parallel connection of capacitor-switch assemblies. A first end node of the series connection is connected to the PWM voltage output node; a second end node of the series connection is connected to electrical ground; each of the capacitor-switch assemblies includes a respective series connection of a respective capacitor and a respective switch; and each switch within the capacitor-switch assemblies is located within the first semiconductor die.

Abstract: A device structure includes a parallel connection of capacitor-switch assemblies located over a substrate. The capacitor-switch assemblies include a first capacitor-switch assembly that includes a first series connection of a first capacitor and a first non-Ohmic switching device, which has a first threshold voltage and includes a first primary switch electrode, a first secondary switch electrode, and a first non-Ohmic switching material portion. The capacitor switch assemblies further include a second capacitor-switch assembly that includes a second series connection of a second capacitor and a second non-Ohmic switching device, which has a second threshold voltage and includes a second primary switch electrode, a second secondary switch electrode, and a second non-Ohmic switching material portion. The second threshold voltage is different from the first threshold voltage. The non-Ohmic switching devices may be conditionally turned on depending on a magnitude of applied voltage spikes.

Abstract: A memory device having a 3D structure provides MFMIS-FET memory cells with a high chip area density. The memory device includes a stack of memory cell layers interleaved with insulating layers. Channel vias penetrate through the stack. Channels of the memory cells are disposed in the channel vias. MFM portions of memory cells are sandwiched between the insulating layers in areas lateral to the channel vias. The MFM portions may be radially distributed from the channel vias and include a floating gate, a ferroelectric layer, and a gate electrode. The gate electrodes associated with a plurality of MFM structures may be united into a word line gate. The ferroelectric layer may wrap around the word line gate, whereby the ferroelectric layer is disposed above and below the word line gate as well as between the word line gate and each of the floating gates.

Abstract: A device structure includes semiconductor devices located on a substrate; metal interconnect structures located in dielectric material layers overlying the semiconductor devices; and a non-Ohmic voltage-triggered switch including a first switch electrode that is electrically connected to one of the semiconductor devices through a subset of the metal interconnect structures, a second switch electrode, and a non-Ohmic switching material portion providing a non-Ohmic current-voltage characteristics and in contact with the first switch electrode and the second switch electrode. The non-Ohmic voltage-triggered switch may be used as an electrostatic discharge (ESD) switch.

Abstract: An embodiment phase change material (PCM) switch may include a phase change material element, a first electrode, a second electrode, and a direct heating element including an ionic resistance change material contacting the phase change material element. The phase change material element may include a phase change material that switches from an electrically conducting phase to an electrically insulating phase or from an electrically insulating phase to an electrically conducting phase by application of a heat pulse generated by the heating element. The PCM switch may further include a switching electrode contacting the ionic resistance change material such that the ionic resistance change material may be switched from a high resistance to a low resistance state by application of voltages to the first electrode, the second electrode, and the switching electrode. Electrical currents within the ionic resistance change material may generate heat that switches the phase change material element.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer, a first floating gate electrode, a first control gate electrode, an erase gate electrode, and a blocking layer. The semiconductor substrate has a first source/drain region. The first semiconductor layer extends upward from the first source/drain region of the semiconductor substrate. The first floating gate electrode surrounds the first semiconductor layer. The first control gate electrode surrounds the first floating gate electrode and the first semiconductor layer. The erase gate electrode is over the first floating gate electrode and the first control gate electrode. The erase gate electrode surrounds the first semiconductor layer. The blocking layer has a first portion between the first floating gate electrode and the first control gate electrode and a second portion between the erase gate electrode and the first semiconductor layer.

Abstract: A method of manufacturing an integrated circuit includes following operations. A stack of a plurality pair of first layers and second layers alternately arranged is formed over a substrate. A plurality of first holes is formed in the stack. An isolation layer is formed to cover sidewalls of the first holes. A plurality of conductive features is formed in the first holes. A plurality of second holes are formed in the stack. Each of the second holes exposes a portion of a sidewall of at least one of the conductive features. A channel layer is formed to cover sidewalls of the second holes and the portions of the sidewalls of the conductive features. The second layers of the stack are replaced with a plurality of gate layers.

Abstract: Device structures and methods for forming the same are provided. A semiconductor structure according to the present disclosure includes a first electrode and a second electrode disposed over a substrate, a heating element disposed over the substrate, a phase-change material layer disposed over the substrate, and an insulator disposed vertically between the heating element and the phase-change material layer. The phase-change material layer includes at least a first segment and a second segment separated from the first segment. Each of the first and second segments overlaps the heating element in a top view. Each of the first and second segments is electrically connected with both the first and second electrodes.

Abstract: A semiconductor device includes a first film, a second film, and a third film that each include a phase change material (PCM) and are arranged with respect to one another along a first lateral direction. The semiconductor device includes a first metal pad, a second metal pad, a third metal pad, and a fourth metal pad. The first and second metal pads are disposed over ends of the first film, respectively, the second and third metal pads are disposed over ends of the second film, respectively, and the third and fourth metal pads are disposed over ends of the third film, respectively. The semiconductor device includes a first heater, a second heater, and a third heater, respectively disposed below the first film, the second film, and the third film.

Abstract: Phase change material (PCM) switches and methods of fabrication thereof that include a phase change material layer and a selector having a first electrode and an ovonic threshold switching (OTS) material layer. The first electrode may selectively apply a bias voltage to the OTS layer, causing localized heating within the OTS layer. The phase change material layer may be in thermal contact with the OTS layer such that the OTS layer may heat an active region of the phase change material layer. By controlling the voltage applied to the first electrode and the resultant heating within the OTS layer, the active region of the phase change material layer may be selectively transitioned between a high resistivity state and a low resistivity state. A PCM switch according to various embodiments may enable low power and fast switching between high resistivity and low resistivity states and reduced parasitic capacitance.

Abstract: A memory cell, an integrated circuit and method of manufacturing the same are provided. The memory device includes a substrate, gate layers and insulating layers, an isolation column, a channel layer, a first conductive feature, a second conductive feature, a storage layer and a pair of isolation structures. The isolation column extends through the gate layers and the insulating layers along a first direction. The channel layer laterally covers the isolation column. The first conductive feature and second conductive feature extend along the first direction and adjacent to the isolation column. The storage layer is disposed between the gate layers and the channel layer. The pair of isolation structures extends along the first direction. The pair of isolation structures includes a first isolation structure disposed between the first conductive feature and the gate layers, and a second isolation structure disposed between the second conductive feature and the gate layers.