Abstract: A memory device is described that includes a three-dimensional array of memory cells having a plurality of levels of memory cells accessed by a plurality of word lines, and a plurality of bit lines. Control circuitry is coupled to the plurality of word lines and the plurality of bit lines. The control circuitry is adapted for programming a selected memory cell in a selected level of the array and on a selected word line, by hot carrier generation assisted FN tunneling, while inhibiting disturb in unselected memory cells in unselected levels and in the selected level and on unselected word lines by self-boosting.

Abstract: A programming bias technique is described for programming a stacked memory structure with a plurality of layers of memory cells. The technique includes the controller circuitry responsive to a program instruction to program data in target cells in a stack of cells at a particular multibit address. The circuitry is configured to use an assignment of cells in the stack of cells to a plurality of sets of cells, and to iteratively execute a set program operation selecting each of the plurality of sets in sequence. Each iteration includes applying inhibit voltages to all of the cells in others of the plurality of sets. Also, each set of layers includes subsets of one or two, and there are at least two layers from other sets separating each of the subsets in one set.

Abstract: A multiple bits per cell memory is operated by applying a one-pass, multiple-level programming, using a single pulse sequence one time (or in one-pass), such as an incremental pulse program sequence, with program verify steps for multiple target program levels, to program multiple bits per cell in a plurality of memory cells. Using these techniques, the number of program pulses required, and the time required for programming the data can be reduced. As a result, an improvement in programming throughput and a reduction in disturbance conditions are achieved. Variants of the one-pass, multiple-level programming operation can be adopted for a variety of memory cell types, memory architectures, programming speeds, and data storage densities.

Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation.

Abstract: A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a resistance. The transistor includes a gate dielectric that is switchable between a plurality of different resistance values. The threshold voltage of the transistor changes according to the resistance value of the gate dielectric. Memory states of the memory cells can thus be associated with respective resistance values of the dielectric layer of the transistor.

Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation.

Abstract: A method of manufacturing resistive memory includes the steps: forming a first implanted stacked structure having a first impurity diffusion layer, a second impurity diffusion layer, and a third impurity diffusion layer in a substrate; etching at least the first implanted stacked structure to form a plurality of second implanted stacked structures, wherein the first impurity diffusion layers are first signal lines; forming a plurality of first insulating layers between the second implanted stacked structures; etching the second implanted stacked structures to form a plurality of third implanted stacked structures, wherein the first signal lines are not etched; forming a plurality of second insulating layers between the third implanted stacked structures; forming a plurality of memory material layers electrically coupled to the third impurity diffusion layers; and forming a plurality of second signal lines perpendicular to the first signal lines and electrically coupled to the memory material layers.

Abstract: A diode memory device has an intermediate structure between the two terminals, such as a p terminal and the n terminal.

Abstract: A memory, comprising a metal portion, a first metal layer and second metal oxide layer is provided. The first metal oxide layer is on the metal portion, and the first metal oxide layer includes N resistance levels. The second metal oxide layer is on the first metal oxide layer, and the second metal oxide layer includes M resistance levels. The memory has X resistance levels and X is less than the summation of M and N, for minimizing a programming disturbance.

Abstract: Metal-oxide based memory devices and methods for operating and manufacturing such devices are described herein. A method for manufacturing a memory device as described herein comprises forming a metal-oxide memory element, and applying an activating energy to the metal-oxide memory element. In embodiments the activating energy can be applied by applying electrical and/or thermal energy to the metal-oxide material.

Abstract: A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a resistance. The transistor includes a gate dielectric that is switchable between a plurality of different resistance values. The threshold voltage of the transistor changes according to the resistance value of the gate dielectric. Memory states of the memory cells can thus be associated with respective resistance values of the dielectric layer of the transistor.

Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein includes a first electrode and a second electrode. The memory device further includes a diode and an anti-fuse metal-oxide memory element comprising aluminum oxide and copper oxide. The diode and the metal-oxide memory element are arranged in electrical series between the first electrode and the second electrode.

Abstract: A diode memory device has an intermediate structure between the two terminals, such as a p terminal and the n terminal.

Abstract: A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 ?, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.

Abstract: A method of fabricating a semiconductor device is provided. The method comprises: (a) providing a first and a second conductor; (b) providing a conductive layer; (c) forming a part of the conductive layer into a data storage layer by a plasma oxidation process, wherein the data storage layer is positioned between the first and the second conductor.

Abstract: A method for operating a memory device includes applying a sequence of bias arrangements across a selected metal-oxide memory element to change among resistance states. The sequence of bias arrangements includes a first set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the first resistance state to a third resistance state, and a second set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the third resistance state to the second resistance state.

Abstract: A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 ?, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.

Abstract: A memory, comprising a metal portion, a first metal layer and second metal oxide layer is provided. The first metal oxide layer is on the metal element, and the first metal oxide layer includes N resistance levels. The second metal oxide layer is on the first metal oxide layer, and the second metal oxide layer includes M resistance levels. The memory has X resistance levels and X is less than the summation of M and N, for minimizing a programming disturbance.

Abstract: A method of manufacturing resistive memory includes the steps: forming a first implanted stacked structure having a first impurity diffusion layer, a second impurity diffusion layer, and a third impurity diffusion layer in a substrate; etching at least the first implanted stacked structure to form a plurality of second implanted stacked structures, wherein the first impurity diffusion layers are first signal lines; forming a plurality of first insulating layers between the second implanted stacked structures; etching the second implanted stacked structures to form a plurality of third implanted stacked structures, wherein the first signal lines are not etched; forming a plurality of second insulating layers between the third implanted stacked structures; forming a plurality of memory material layers electrically coupled to the third impurity diffusion layers; and forming a plurality of second signal lines perpendicular to the first signal lines and electrically coupled to the memory material layers.

Abstract: A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 ?, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.