Abstract: An apparatus and method for detecting an intensity of radiation in a process chamber, such as an ultraviolet curing process chamber, is disclosed. An exemplary apparatus includes a process chamber having a radiation source therein, wherein the radiation source is configured to emit radiation within the process chamber; a radiation sensor attached to the process chamber; and an optical fiber coupled with the radiation source and the radiation sensor, wherein the optical fiber is configured to transmit a portion of the emitted radiation to the radiation sensor, and the radiation sensor is configured to detect an intensity of the portion of the emitted radiation via the optical fiber.

Abstract: A method and system for aligning robotic wafer transfer systems provides a wafer cassette having one or more wafer slots having portions covered with an electrically conductive material and a sensor that is in electrical communication with the electrically conductive material. When a wafer is loaded into a wafer cassette such as may be contained within a wafer transfer module such as a FOUP, an indication of position is delivered to the sensor which detects the alignment and indicates if the loaded wafer undesirably contacts either or both of the opposed grooves that form the wafer slot of the wafer cassette. An indication of the wafer's position may be provided from the sensor to a controller that delivers a signal for aligning the wafer transfer blade of the wafer transfer robot responsive to the signal indicative of position.

Abstract: A method and system for aligning robotic wafer transfer systems provides a wafer cassette having one or more wafer slots having portions covered with an electrically conductive material and a sensor that is in electrical communication with the electrically conductive material. When a wafer is loaded into a wafer cassette such as may be contained within a wafer transfer module such as a FOUP, an indication of position is delivered to the sensor which detects the alignment and indicates if the loaded wafer undesirably contacts either or both of the opposed grooves that form the wafer slot of the wafer cassette. An indication of the wafer's position may be provided from the sensor to a controller that delivers a signal for aligning the wafer transfer blade of the wafer transfer robot responsive to the signal indicative of position.

Abstract: A low temperature cofired ceramic material mainly includes that mixed evenly with high thermal conductivity ceramic materials (AlN) and Borosilicate powder glass materials.

Abstract: Polymers containing triarylsilyl(meth)acryloyl units are erodible in seawater and can be used to formulate antifouling marine paints. The polymers are characterized by low levels of triarylsilyl(meth) acrylate units and an erosion rate in seawater of 2 to about 15 microns per month.

Abstract: Copolymers of at least three monomer units selected from the group consisting of fluorinated acrylic (methacrylic) monomers, triorganosilylacrylic (e.g. trimethylsilyl methacrylate) monomers and acrylic monomers not containing an organosilyl moiety, (e.g. methyl methacrylate) and optionally containing from 0-5 weight percent of a cross-linking agent are novel compositions useful as polymeric binders in long life marine antifoulant coatings.

Abstract: Polymers containing triarylsilyl(meth)acryloyl units are erodible in seawater and can be used to formulate antifouling marine paints. The polymers are characterized by low levels of triarylsilyl(meth) acrylate units and an erosion rate in seawater of 2 to about 15 microns per month.

Abstract: Copolymers containing triarylsilyl(meth)acryloyl units are erodible in seawater and can be used to formulate antifouling marine paints. The copolymers are characterized by low levels of triarylsilyl(meth)acrylate units and an erosion rate in seawater of 2 to about 15 microns per month.

Abstract: Copolymers of at least three monomer units selected from the group consisting of fluorinated acrylic (methacrylic) monomers, triorganosilylacrylic (e.g. trimethylsilyl methacrylate) monomers and acrylic monomers not containing an organosilyl moiety, (e.g. methyl methacrylate) and optionally containing from 0-5 weight percent of a cross-linking agent are novel compositions useful as polymeric binders in long life marine antifoulant coatings.

Abstract: The present invention discloses a method for forming shallow trench isolation in a semiconductor device, particularly a nonvolatile memory device. A dielectric layer, an amorphous silicon layer, and a mask layer are sequentially formed over a substrate. Isolation trenches are etched in the substrate through the layers. An oxide layer is thermally grown lining the sidewalls of the amorphous silicon layer and the trenches. Due to the lower oxidation rate of amorphous silicon, the liner oxide layer is thinner at the position lining the amorphous silicon layer than at the position lining the trench. The trenches are filled with an isolation layer to form shallow trench isolation (STI) structures. After removing the mask layer, the amorphous silicon layer can be converted into a polysilicon layer to serve as a floating gate for a nonvolatile memory device.

Abstract: A process for creating a storage node electrode for a DRAM capacitor structure, featuring increased surface area accomplished using an HSG silicon layer as the top layer for the storage node electrode, has been developed. The process features the use of a composite buffer layer of undoped and lightly doped amorphous silicon layers, located overlying a heavily doped amorphous silicon layer, and then followed by the deposition of HSG silicon seeds. A first anneal cycle then allows formation of an undoped HSG silicon layer to be realized on the underlying heavily doped amorphous silicon layer, via consumption of the HSG seeds, and of the composite buffer layer of undoped and lightly doped amorphous silicon layers. A second anneal cycle then allows dopant from the underlying heavily doped amorphous silicon layer to reach the undoped HSG silicon layer, resulting in a doped HSG silicon layer.

Abstract: A process for creating a crown shaped storage node electrode, covered with an HSG silicon layer, used to increase the surface area, and thus the capacitance of, high density, DRAM designs, has been developed. The process features creating a crown shaped storage node shape, from a composite amorphous silicon layer, wherein the composite amorphous silicon layer is comprised of a heavily doped amorphous silicon layer, used to alleviate capacitance depletion phenomena, sandwiched between undoped, or lightly doped, amorphous silicon layers, used to selectively accept the overlying HSG silicon layer. The process also features the use an HF vapor pre-clean procedure, followed by an in situ, selective deposition of HSG silicon seeds, in a conventional LPCVD chamber, prior to anneal cycle used to form the HSG silicon layer.

Abstract: A method of forming a MOS transistor having a p.sup.+ -polysilicon gate includes doping an amorphous silicon layer with phosphorus, thereby forming a n.sup.- amorphous silicon layer atop of a gate oxide. The n.sup.- amorphous silicon layer is then doped with boron to convert the n.sup.- amorphous silicon layer into a p.sup.+ -amorphous silicon layer. The p.sup.+ -amorphous silicon layer is then thermally treated to convert the p.sup.+ -amorphous silicon layer into a p.sup.+ -polysilicon layer. The p.sup.+ -polysilicon layer is then patterned into a gate for a MOS transistor. The phosphorus ions in the p.sup.+ -polysilicon help to fix the boron ions in the polysilicon gate, thereby reducing the diffusion of the boron ions and penetration of boron into the gate oxide.

Abstract: A method for creating stacked capacitor structures, with increased surface area, obtained using storage node electrode structures comprised of an HSG silicon layer, on a heavily doped amorphous silicon layer, both overlying polysilicon storage node shapes, has been developed. A dilute hydrofluoric acid pre-clean procedure is used prior to depositing a heavily doped amorphous silicon layer, on underlying polysilicon storage node shapes. An overlying second amorphous silicon layer is in situ deposited, in the same furnace used for the prior deposition of heavily doped amorphous silicon layer, followed by an in situ seeding/annealing procedure, converting the second amorphous silicon layer to an HSG silicon layer. This invention features the use of the acid pre-clean, to improve adhesion of the heavily doped amorphous silicon layer, to underlying polysilicon storage node shapes.

Abstract: The present invention relates to a method that reduces the thermal gradient at polymorphic transformation of polysilicon. The cooling rate of conventional furnaces is too rapid in currently used processes. The thermal process includes high stress from polymorphic transformation, which causes the peeling of a polysilicon film and microcracking of the quartz tube and wafer boat. The present invention suggests steps following of reducing cracks of polysilicon in a quartz tube and boat. At first, determines the temperature of polymorphic transformation of said quartz tube and boat. Next, reduces the temperature gradient during heating or cooling of said quartz tube and boat during said temperature of polysilicon transformation. Furthermore, the heating or cooling rates of the furnace is limited to the range of 0.1.degree.-2.degree. C./min to reduce the temperature gradient inside the furnace tube.

Abstract: In the polymerization of vinyl chloride monomer or a mixture of vinyl monomers having vinyl chlorides as a main component, the deposition of polymer scale on the inner walls of the polymerization vessel can be effectively reduced by coating the internal surfaces of the reactor with first, a condensation polymer of a polyhydric phenol and an aldehyde and second, a crosslinking agent to increase the insolubility of the polymeric material.