Patents by Inventor Kuo-Tung Chang
Kuo-Tung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10644016Abstract: A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (FET) comprising a semiconductor substrate, a doped region in the semiconductor substrate, and a gate structure on the semiconductor substrate and a method of fabricating the same are also discussed. The doped region comprises a first lateral dimension along a first direction. The gate structure comprises a charge trapping dielectric region and a charge trapping conductive region in contact with the charge trapping dielectric region.Type: GrantFiled: October 30, 2014Date of Patent: May 5, 2020Assignee: Cypress Semiconductor CorporationInventors: Kuo Tung Chang, Shenqing Fang, Timothy Thurgate
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Patent number: 10622370Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.Type: GrantFiled: September 25, 2015Date of Patent: April 14, 2020Assignee: Monterey Research, LLCInventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, Youseok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Ramesh Joshi, Hapreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang
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Patent number: 10516044Abstract: A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.Type: GrantFiled: October 21, 2013Date of Patent: December 24, 2019Assignee: Cypress Semiconductor CorporationInventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
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Publication number: 20190386109Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.Type: ApplicationFiled: July 19, 2019Publication date: December 19, 2019Applicant: Cypress Semiconductor CorporationInventors: Shenqing Fang, Chun Chen, Unsoon KIM, Mark Ramsbey, Kuo Tung Chang, Sameer HADDAD, James Pak
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Publication number: 20190385853Abstract: A semiconductor device having a substrate, a dielectric layer, a polycrystalline silicon (“poly”) resistor, a drain, and a source is disclosed. After implantation, the poly resistor may have a lateral doping profile with two peaks, one near each edge of the poly resistor, and a trough near the middle of the poly resistor. Such a doping profile can allow the poly resistor to have a resistance that is insensitive to small variations in critical dimension of the poly resistor. The resistance of the poly resistor may be determined by the doping dose of the tilted implant used to form the poly resistor. The tilted implant may be used to form the drain and the source of a transistor substantially simultaneously as forming the poly resistor.Type: ApplicationFiled: June 26, 2019Publication date: December 19, 2019Applicant: Cypress Semiconductor CorporationInventors: Shenqing Fang, Timothy Thurgate, Kuo Tung Chang
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Patent number: 10497710Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed in a first region of a substrate, and a non-volatile memory (NVM) cell including a select gate and a memory gate formed in a first recess in a second region of the same substrate, wherein the recess is recessed relative to a first surface of the substrate. The metal-gate logic transistor includes a planarized surface above and substantially parallel to the first surface, and top surfaces of the select gate and memory gate are approximately at or below an elevation of the planarized surface of the metal-gate. Generally, at least one of the top surfaces of the select gate or the memory gate includes a silicide formed thereon. Other embodiments are also disclosed.Type: GrantFiled: October 12, 2017Date of Patent: December 3, 2019Assignee: Cypress Semiconductor CorporationInventors: Sung-Taeg Kang, James Pak, Unsoon Kim, Inkuk Kang, Chun Chen, Kuo-Tung Chang
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Patent number: 10446245Abstract: A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.Type: GrantFiled: December 20, 2018Date of Patent: October 15, 2019Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, Yoram Betser, Kuo Tung Chang, Amichai Givant, Shivananda Shetty, Shenqing Fang
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Publication number: 20190304990Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.Type: ApplicationFiled: March 4, 2019Publication date: October 3, 2019Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, James Pak, Unsoon KIM, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Publication number: 20190279729Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.Type: ApplicationFiled: February 6, 2019Publication date: September 12, 2019Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, Kuo Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh
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Patent number: 10403731Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.Type: GrantFiled: June 15, 2018Date of Patent: September 3, 2019Assignee: Cypress Semiconductor CorporationInventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark Ramsbey, Kuo Tung Chang, Sameer Haddad, James Pak
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Publication number: 20190198124Abstract: A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.Type: ApplicationFiled: December 20, 2018Publication date: June 27, 2019Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, Yoram Betser, Kuo Tung Chang, Amichai Givant, Shivananda Shetty, Shenqing Fang
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Patent number: 10242996Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.Type: GrantFiled: December 20, 2017Date of Patent: March 26, 2019Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Patent number: 10236299Abstract: A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell.Type: GrantFiled: June 23, 2016Date of Patent: March 19, 2019Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, Kuo-Tung Chang, Shenqing Fang
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Patent number: 10229745Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, an apparatus comprises a flash memory device coupled to a microprocessor. The flash memory device comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). A control circuit in the flash memory device is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory device, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the flash memory device.Type: GrantFiled: January 23, 2018Date of Patent: March 12, 2019Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, Kuo-Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh
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Patent number: 10192627Abstract: A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.Type: GrantFiled: April 17, 2018Date of Patent: January 29, 2019Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, Yoram Betser, Kuo Tung Chang, Amichai Givant, Shivananda Shetty, Shenqing Fang
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Publication number: 20190027487Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.Type: ApplicationFiled: December 20, 2017Publication date: January 24, 2019Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Publication number: 20190027484Abstract: Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.Type: ApplicationFiled: December 20, 2017Publication date: January 24, 2019Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Publication number: 20180366551Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.Type: ApplicationFiled: June 15, 2018Publication date: December 20, 2018Applicant: Cypress Semiconductor CorporationInventors: Shenqing Fang, Chun Chen, Unsoon KIM, Mark Ramsbey, Kuo Tung Chang, Sameer HADDAD, James Pak
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Patent number: 10141393Abstract: Integrated capacitor structures and methods for fabricating same are provided. In an embodiment, the integrated capacitor structures exploit the capacitance that can be formed in a plane that is perpendicular to that of the substrate, resulting in three-dimensional capacitor structures. This allows for integrated capacitor structures with higher capacitance to be formed over relatively small substrate areas. Embodiments are suitable for use by charge pumps and can be fabricated to have more or less capacitance as desired by the application.Type: GrantFiled: March 3, 2016Date of Patent: November 27, 2018Assignee: Cypress Semiconductor CorporationInventors: Mark Ramsbey, Unsoon Kim, Shenqing Fang, Chun Chen, Kuo Tung Chang
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Publication number: 20180323314Abstract: A split gate device that includes a memory gate and a select gate disposed side by side, a dielectric structure having a first portion disposed between the memory gate and a substrate and a second portion disposed along an inner sidewall of the select gate to separate the select gate from the memory gate, and a spacer formed over the select gate along an inner sidewall of the memory gate. Other embodiments of embedded split gate devices including high voltage and low voltage transistors are also disclosed.Type: ApplicationFiled: April 10, 2018Publication date: November 8, 2018Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, Shenqing Fang, Unsoon KIM, Mark T. Ramsbey, Kuo Tung Chang, Sameer S. HADDAD