Patents by Inventor Kuo-Tung Chang
Kuo-Tung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12146502Abstract: An impeller and a fan are provided. The impeller includes a hub, a plurality of first blades, a plurality of second blades and a connecting member. The plurality of first blades are disposed around the hub separately. Each first blade is connected with a periphery of the hub. The plurality of second blades are disposed around the hub separately. Each second blade is disposed away from the periphery of the hub and located between two adjacent first blades of the plurality of first blades. The connecting member is disposed around the hub and penetrated through the plurality of first blades and the plurality of second blades. The connecting member is not in contact with a first edge of any side of each first blade. The connecting member is not in contact with a second edge of any side of each second blade.Type: GrantFiled: September 2, 2020Date of Patent: November 19, 2024Assignee: Delta Electronics, Inc.Inventors: Kuo-Tung Hsu, Shun-Chen Chang, Chao-Fu Yang, Li-Han Hung
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Patent number: 12029041Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.Type: GrantFiled: June 26, 2023Date of Patent: July 2, 2024Assignee: INFINEON TECHNOLOGIES LLCInventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Publication number: 20240206183Abstract: A semiconductor device and methods of fabrication the same are disclosed. In one embodiment, the semiconductor device may include a non-volatile memory (NVM) cell including a memory gate stack and a select gate stack separated by an inter-gate dielectric disposed in a memory region of a substrate, a low voltage field-effect transistor (LVFET) including a first high-K metal-gate (HKMG) stack disposed in a peripheral region of the substrate, and a high voltage field-effect transistor (HVFET) including a second HKMG stack disposed in the peripheral region, in which top surfaces of the memory gate stack and the select gate stack of the NVM cell, the LVFET, and the HVFET have an approximately same elevation from the substrate or are substantially co-planar. Other embodiments are also disclosed within.Type: ApplicationFiled: February 29, 2024Publication date: June 20, 2024Applicant: Cypress Semiconductor CorporationInventors: Chun CHEN, James PAK, Unsoon KIM, Inkuk KANG, Sung-Taeg KANG, Kuo Tung CHANG
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Publication number: 20240008279Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.Type: ApplicationFiled: June 26, 2023Publication date: January 4, 2024Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, James Pak, Unsoon KIM, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Patent number: 11830942Abstract: In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.Type: GrantFiled: March 4, 2021Date of Patent: November 28, 2023Assignee: Infineon Technologies LLCInventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
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Patent number: 11690227Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.Type: GrantFiled: May 18, 2021Date of Patent: June 27, 2023Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Publication number: 20220302297Abstract: In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.Type: ApplicationFiled: March 4, 2021Publication date: September 22, 2022Applicant: Cypress Semiconductor CorporationInventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
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Patent number: 11342429Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.Type: GrantFiled: September 30, 2020Date of Patent: May 24, 2022Assignee: Cypress Semiconductor CorporationInventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark T. Ramsbey, Kuo Tung Chang, Sameer S. Haddad, James Pak
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Patent number: 11257675Abstract: A semiconductor device having a substrate, a dielectric layer, a polycrystalline silicon (“poly”) resistor, a drain, and a source is disclosed. After implantation, the poly resistor may have a lateral doping profile with two peaks, one near each edge of the poly resistor, and a trough near the middle of the poly resistor. Such a doping profile can allow the poly resistor to have a resistance that is insensitive to small variations in critical dimension of the poly resistor. The resistance of the poly resistor may be determined by the doping dose of the tilted implant used to form the poly resistor. The tilted implant may be used to form the drain and the source of a transistor substantially simultaneously as forming the poly resistor.Type: GrantFiled: June 26, 2019Date of Patent: February 22, 2022Assignee: Cypress Semiconductor CorporationInventors: Shenqing Fang, Timothy Thurgate, Kuo Tung Chang
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Publication number: 20210296343Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.Type: ApplicationFiled: May 18, 2021Publication date: September 23, 2021Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, James Pak, Unsoon KIM, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Patent number: 11081194Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.Type: GrantFiled: May 6, 2020Date of Patent: August 3, 2021Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, Kuo Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh
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Publication number: 20210134811Abstract: Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.Type: ApplicationFiled: November 20, 2020Publication date: May 6, 2021Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Publication number: 20210091198Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.Type: ApplicationFiled: September 30, 2020Publication date: March 25, 2021Applicant: Cypress Semiconductor CorporationInventors: Shenqing Fang, Chun Chen, Unsoon KIM, Mark T. Ramsbey, Kuo Tung Chang, Sameer S. HADDAD, James Pak
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Patent number: 10944000Abstract: In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.Type: GrantFiled: December 3, 2019Date of Patent: March 9, 2021Assignee: Cypress Semiconductor CorporationInventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
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Patent number: 10923601Abstract: A split gate device that includes a memory gate and a select gate disposed side by side, a dielectric structure having a first portion disposed between the memory gate and a substrate and a second portion disposed along an inner sidewall of the select gate to separate the select gate from the memory gate, and a spacer formed over the select gate along an inner sidewall of the memory gate. Other embodiments of embedded split gate devices including high voltage and low voltage transistors are also disclosed.Type: GrantFiled: April 10, 2018Date of Patent: February 16, 2021Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, Shenqing Fang, Unsoon Kim, Mark T. Ramsbey, Kuo Tung Chang, Sameer S. Haddad
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Patent number: 10872898Abstract: Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.Type: GrantFiled: December 20, 2017Date of Patent: December 22, 2020Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
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Patent number: 10818761Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.Type: GrantFiled: July 19, 2019Date of Patent: October 27, 2020Assignee: Cypress Semiconductor CorporationInventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark Ramsbey, Kuo Tung Chang, Sameer Haddad, James Pak
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Publication number: 20200303023Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.Type: ApplicationFiled: May 6, 2020Publication date: September 24, 2020Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, Kuo Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh
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Publication number: 20200212215Abstract: In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.Type: ApplicationFiled: December 3, 2019Publication date: July 2, 2020Applicant: Cypress Semiconductor CorporationInventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
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Patent number: 10685724Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.Type: GrantFiled: February 6, 2019Date of Patent: June 16, 2020Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, Kuo Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh