Patents by Inventor Kuo-Tung Chang

Kuo-Tung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240008279
    Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.
    Type: Application
    Filed: June 26, 2023
    Publication date: January 4, 2024
    Applicant: Cypress Semiconductor Corporation
    Inventors: Chun Chen, James Pak, Unsoon KIM, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
  • Patent number: 11830942
    Abstract: In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: November 28, 2023
    Assignee: Infineon Technologies LLC
    Inventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
  • Patent number: 11690227
    Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: June 27, 2023
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
  • Publication number: 20220302297
    Abstract: In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.
    Type: Application
    Filed: March 4, 2021
    Publication date: September 22, 2022
    Applicant: Cypress Semiconductor Corporation
    Inventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
  • Patent number: 11342429
    Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 24, 2022
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark T. Ramsbey, Kuo Tung Chang, Sameer S. Haddad, James Pak
  • Patent number: 11257675
    Abstract: A semiconductor device having a substrate, a dielectric layer, a polycrystalline silicon (“poly”) resistor, a drain, and a source is disclosed. After implantation, the poly resistor may have a lateral doping profile with two peaks, one near each edge of the poly resistor, and a trough near the middle of the poly resistor. Such a doping profile can allow the poly resistor to have a resistance that is insensitive to small variations in critical dimension of the poly resistor. The resistance of the poly resistor may be determined by the doping dose of the tilted implant used to form the poly resistor. The tilted implant may be used to form the drain and the source of a transistor substantially simultaneously as forming the poly resistor.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: February 22, 2022
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shenqing Fang, Timothy Thurgate, Kuo Tung Chang
  • Publication number: 20210296343
    Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.
    Type: Application
    Filed: May 18, 2021
    Publication date: September 23, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Chun Chen, James Pak, Unsoon KIM, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
  • Patent number: 11081194
    Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: August 3, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Kuo Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh
  • Publication number: 20210134811
    Abstract: Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.
    Type: Application
    Filed: November 20, 2020
    Publication date: May 6, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
  • Publication number: 20210091198
    Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.
    Type: Application
    Filed: September 30, 2020
    Publication date: March 25, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Shenqing Fang, Chun Chen, Unsoon KIM, Mark T. Ramsbey, Kuo Tung Chang, Sameer S. HADDAD, James Pak
  • Patent number: 10944000
    Abstract: In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: March 9, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
  • Patent number: 10923601
    Abstract: A split gate device that includes a memory gate and a select gate disposed side by side, a dielectric structure having a first portion disposed between the memory gate and a substrate and a second portion disposed along an inner sidewall of the select gate to separate the select gate from the memory gate, and a spacer formed over the select gate along an inner sidewall of the memory gate. Other embodiments of embedded split gate devices including high voltage and low voltage transistors are also disclosed.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 16, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Shenqing Fang, Unsoon Kim, Mark T. Ramsbey, Kuo Tung Chang, Sameer S. Haddad
  • Patent number: 10872898
    Abstract: Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: December 22, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
  • Patent number: 10818761
    Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: October 27, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark Ramsbey, Kuo Tung Chang, Sameer Haddad, James Pak
  • Publication number: 20200303023
    Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.
    Type: Application
    Filed: May 6, 2020
    Publication date: September 24, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Kuo Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh
  • Publication number: 20200212215
    Abstract: In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.
    Type: Application
    Filed: December 3, 2019
    Publication date: July 2, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
  • Patent number: 10685724
    Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: June 16, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Kuo Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh
  • Publication number: 20200146792
    Abstract: This invention relates to a finger wearable interdental cleaning apparatus comprising finger hooks and attachable toothpick. The finger hooks are mounted on finger joint areas with the toothpick being attached to the body of the finger hooks. By using finger joint areas to control the movement of the toothpick, it frees up the finger tips for holding the toothpick such that all fingers can be used to cover the mouth area when using the toothpick. The mouth area is covered by the same hand operating the toothpick. It eliminates the need to use the second hand to cover the mouth area when the first hand is operating the toothpick. This makes the tooth cleaning more convenient and better etiquette.
    Type: Application
    Filed: November 14, 2018
    Publication date: May 14, 2020
    Applicant: UMECK LLC
    Inventors: Michael Chang, Kuo Tung Chang
  • Patent number: 10644016
    Abstract: A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (FET) comprising a semiconductor substrate, a doped region in the semiconductor substrate, and a gate structure on the semiconductor substrate and a method of fabricating the same are also discussed. The doped region comprises a first lateral dimension along a first direction. The gate structure comprises a charge trapping dielectric region and a charge trapping conductive region in contact with the charge trapping dielectric region.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: May 5, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kuo Tung Chang, Shenqing Fang, Timothy Thurgate
  • Patent number: 10622370
    Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 14, 2020
    Assignee: Monterey Research, LLC
    Inventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, Youseok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Ramesh Joshi, Hapreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang