Patents by Inventor Kuo-Tung Chang
Kuo-Tung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180261295Abstract: A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.Type: ApplicationFiled: April 17, 2018Publication date: September 13, 2018Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, Yoram Betser, Kuo Tung Chang, Amichai GIVANT, Shivananda Shetty, Shenqing Fang
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Publication number: 20180190361Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, an apparatus comprises a flash memory device coupled to a microprocessor. The flash memory device comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). A control circuit in the flash memory device is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory device, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the flash memory device.Type: ApplicationFiled: January 23, 2018Publication date: July 5, 2018Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, Kuo-Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh
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Patent number: 10014380Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.Type: GrantFiled: September 29, 2016Date of Patent: July 3, 2018Assignee: Cypress Semiconductor CorporationInventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark Ramsbey, Kuo Tung Chang, Sameer Haddad, James Pak
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Publication number: 20180166458Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed in a first region of a substrate, and a non-volatile memory (NVM) cell including a select gate and a memory gate formed in a first recess in a second region of the same substrate, wherein the recess is recessed relative to a first surface of the substrate. The metal-gate logic transistor includes a planarized surface above and substantially parallel to the first surface, and top surfaces of the select gate and memory gate are approximately at or below an elevation of the planarized surface of the metal-gate. Generally, at least one of the top surfaces of the select gate or the memory gate includes a silicide formed thereon. Other embodiments are also disclosed.Type: ApplicationFiled: October 12, 2017Publication date: June 14, 2018Applicant: Cypress Semiconductor CorporationInventors: Sung-Taeg Kang, James Pak, Unsoon KIM, Inkuk Kang, Chun Chen, Kuo-Tung Chang
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Publication number: 20180166141Abstract: A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.Type: ApplicationFiled: March 28, 2017Publication date: June 14, 2018Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, Yoram Betser, Kuo-Tung Chang, Amichai GIVANT, Shivananda SHETTY, Shenqing Fang
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Patent number: 9997253Abstract: A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.Type: GrantFiled: March 28, 2017Date of Patent: June 12, 2018Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, Yoram Betser, Kuo-Tung Chang, Amichai Givant, Shivananda Shetty, Shenqing Fang
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Patent number: 9966477Abstract: Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split gate device is a charge trapping split gate device, which includes a charge trapping layer. In another embodiment, the split gate device is a non-volatile memory cell, which can be formed according to embodiments as standalone or embedded with a periphery device.Type: GrantFiled: December 14, 2012Date of Patent: May 8, 2018Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, Shenqing Fang, Unsoon Kim, Mark T. Ramsbey, Kuo Tung Chang, Sameer S. Haddad
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Patent number: 9922833Abstract: Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming a dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.Type: GrantFiled: December 16, 2015Date of Patent: March 20, 2018Assignee: Cypress Semiconductor CorporationInventors: Mark Ramsbey, Chun Chen, Sameer Haddad, Kuo Tung Chang, Unsoon Kim, Shenqing Fang, Yu Sun, Calvin Gabriel
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Patent number: 9917166Abstract: A semiconductor device includes a substrate comprising a source region and a drain region, a bit storing element formed on the substrate, a memory gate structure, a first insulating layer formed on the substrate, a second insulating layer formed on the substrate, and a select gate structure formed on the first insulating layer. The second insulating layer is formed on the memory gate structure and the select gate structure and between the memory gate structure and the select gate structure.Type: GrantFiled: June 13, 2016Date of Patent: March 13, 2018Assignee: Cypress Semiconductor CorporationInventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark Ramsbey, Kuo Tung Chang, Sameer Haddad, James Pak
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Patent number: 9881683Abstract: Techniques for suppression of program disturb in memory devices are described herein. In an example embodiment, a memory device comprises a flash memory array coupled to a control circuit. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). The control circuit is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory array, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the memory device.Type: GrantFiled: April 25, 2017Date of Patent: January 30, 2018Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, Kuo-Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh
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Patent number: 9853039Abstract: A semiconductor device including a non-volatile memory (NVM) cell and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed on a logic region of a substrate, and the NVM cell integrally formed in a first recess in a memory region of the same substrate, wherein the first recess is recessed relative to a first surface of the substrate in the logic region. Generally, the metal-gate logic transistor further including a planarized surface above and substantially parallel to the first surface of the substrate in the logic region, and the NVM cell is arranged below an elevation of the planarized surface of the metal-gate. In some embodiments, logic transistor is a High-k Metal-gate (HKMG) logic transistor with a gate structure including a metal-gate and a high-k gate dielectric. Other embodiments are also disclosed.Type: GrantFiled: March 29, 2017Date of Patent: December 26, 2017Assignee: Cypress Semiconductor CorporationInventors: Sung-Taeg Kang, James Pak, Unsoon Kim, Inkuk Kang, Chun Chen, Kuo-Tung Chang
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Patent number: 9818755Abstract: A semiconductor device including a non-volatile memory (NVM) cell and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed on a logic region of a substrate, and the NVM cell integrally formed in a first recess in a memory region of the same substrate, wherein the first recess is recessed relative to a first surface of the substrate in the logic region. Generally, the metal-gate logic transistor further including a planarized surface above and substantially parallel to the first surface of the substrate in the logic region, and the NVM cell is arranged below an elevation of the planarized surface of the metal-gate. In some embodiments, logic transistor is a High-k Metal-gate (HKMG) logic transistor with a gate structure including a metal-gate and a high-k gate dielectric. Other embodiments are also disclosed.Type: GrantFiled: March 29, 2017Date of Patent: November 14, 2017Assignee: Cypress Semiconductor CorporationInventors: Sung-Taeg Kang, James Pak, Unsoon Kim, Inkuk Kang, Chun Chen, Kuo-Tung Chang
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Publication number: 20170141201Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.Type: ApplicationFiled: September 29, 2016Publication date: May 18, 2017Inventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark Ramsbey, Kuo Tung Chang, Sameer Haddad, James Pak
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Patent number: 9508736Abstract: A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell.Type: GrantFiled: October 17, 2013Date of Patent: November 29, 2016Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, Kuo-Tung Chang, Shenqing Fang
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Publication number: 20160307916Abstract: A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell.Type: ApplicationFiled: June 23, 2016Publication date: October 20, 2016Inventors: Chun Chen, Kuo-Tung Chang, Shenqing Fang
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Publication number: 20160293720Abstract: A semiconductor device includes a substrate comprising a source region and a drain region, a bit storing element formed on the substrate, a memory gate structure, a first insulating layer formed on the substrate, a second insulating layer formed on the substrate, and a select gate structure formed on the first insulating layer. The second insulating layer is formed on the memory gate structure and the select gate structure and between the memory gate structure and the select gate structure.Type: ApplicationFiled: June 13, 2016Publication date: October 6, 2016Inventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark Ramsbey, Kuo Tung CHANG, Sameer HADDAD, James Pak
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Publication number: 20160218113Abstract: Semiconductor devices and methods of manufacturing thereof are described. According to an example embodiment, a semiconductor device comprises: a substrate comprising a core region and a peripheral region, where the core region is adjacent to the peripheral region; a memory array comprising non-volatile memory cells that are located in the core region of the substrate; a high-voltage control logic comprising high-voltage transistors that are located in the peripheral region of the substrate; and a low-voltage control logic comprising low-voltage transistors that are located in the peripheral region of the substrate.Type: ApplicationFiled: April 1, 2016Publication date: July 28, 2016Inventors: Kuo Tung CHANG, Chun Chen, Shenqing Fang
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Patent number: 9368606Abstract: Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, a semiconductor device includes a memory gate disposed in a first region of the semiconductor device. The memory gate may include a first gate conductor layer disposed over a charge trapping dielectric. A select gate may be disposed in the first region of the semiconductor device adjacent to a sidewall of the memory gate. A sidewall dielectric may be disposed between the sidewall of the memory gate and the select gate. Additionally, the device may include a logic gate disposed in a second region of the semiconductor device that comprises the first gate conductor layer.Type: GrantFiled: December 14, 2012Date of Patent: June 14, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark Ramsbey, Kuo Tung Chang, Sameer Haddad, James Pak
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Patent number: 9368588Abstract: Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region. A select gate can be formed in the memory region of the device and a first logic gate formed in the logic region. A charge trapping dielectric can then be disposed and removed from a second logic region. A gate conductor layer can then be disposed on the device and etched to define a memory gate on the sidewall of the select gate and a second logic gate in the second logic region.Type: GrantFiled: September 12, 2014Date of Patent: June 14, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Kuo Tung Chang, Chun Chen, Shenqing Fang
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Publication number: 20160126250Abstract: A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (FET) comprising a semiconductor substrate, a doped region in the semiconductor substrate, and a gate structure on the semiconductor substrate and a method of fabricating the same are also discussed. The doped region comprises a first lateral dimension along a first direction. The gate structure comprises a charge trapping dielectric region and a charge trapping conductive region in contact with the charge trapping dielectric region.Type: ApplicationFiled: October 30, 2014Publication date: May 5, 2016Applicant: Spansion LLCInventors: Kuo Tung CHANG, Shenqing Fang, Timothy Thurgate