Patents by Inventor Kuo-Tung Sung
Kuo-Tung Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9607121Abstract: A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.Type: GrantFiled: August 21, 2014Date of Patent: March 28, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-Lung Hsueh, Chih-Ping Chao, Chewn-Pu Jou, Yung-Chow Peng, Harry-Hak-Lay Chuang, Kuo-Tung Sung
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Publication number: 20150020039Abstract: A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.Type: ApplicationFiled: August 21, 2014Publication date: January 15, 2015Inventors: Fu-Lung HSUEH, Chih-Ping CHAO, Chewn-Pu JOU, Yung-Chow PENG, Harry-Hak-Lay CHUANG, Kuo-Tung SUNG
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Patent number: 8847321Abstract: A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.Type: GrantFiled: April 26, 2010Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-Lung Hsueh, Chih-Ping Chao, Chewn-Pu Jou, Yung-Chow Peng, Harry-Hak-Lay Chuang, Kuo-Tung Sung
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Patent number: 8217469Abstract: The present disclosure provides a device in an integrated circuit. The device includes an active region in a semiconductor substrate; an isolation region adjacent the active region; a gate disposed on the active region and extending to the isolation region in a first direction; and a gate contact disposed within the isolation region, having a portion directly overlying and contacting the gate, and having a geometry horizontally extending to a first dimension in the first direction and a second dimension in a second direction approximately perpendicular to the first direction. The first dimension is greater than the second dimension.Type: GrantFiled: February 8, 2010Date of Patent: July 10, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, Yuh-Jier Mii, Kuo-Tung Sung, Li-Chun Tien
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Publication number: 20110215420Abstract: A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.Type: ApplicationFiled: April 26, 2010Publication date: September 8, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Lung HSUEH, Chih-Ping Chao, Chewn-Pu Jou, Yung-Chow Peng, Harry-Hak-Lay Chuang, Kuo-Tung Sung
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Publication number: 20110140203Abstract: The present disclosure provides a device in an integrated circuit. The device includes an active region in a semiconductor substrate; an isolation region adjacent the active region; a gate disposed on the active region and extending to the isolation region in a first direction; and a gate contact disposed within the isolation region, having a portion directly overlying and contacting the gate, and having a geometry horizontally extending to a first dimension in the first direction and a second dimension in a second direction approximately perpendicular to the first direction. The first dimension is greater than the second dimension.Type: ApplicationFiled: February 8, 2010Publication date: June 16, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Chin Hou, Yuh-Jier Mii, Kuo-Tung Sung, Li-Chun Tien
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Patent number: 6469341Abstract: A method and resulting integrated circuit device (100) such as a flash memory device and resulting cell. The method includes a step of providing a substrate (115), which has an active region overlying a thin layer of dielectric material (113). The method uses a step of forming a floating gate layer (107) overlying the thin layer of dielectric material (113), which is commonly termed a “tunnel oxide” layer, but is not limited to such a layer or material. The floating gate layer (107) has novel geometric features including slant edges (121), which extend to the dielectric material (123). The slant edges (121) create a smaller geometric area for the tunnel oxide region relative to the area between the floating gate layer and the control gate layer.Type: GrantFiled: July 25, 2000Date of Patent: October 22, 2002Assignee: Mosel Vitelic, Inc.Inventors: Kuo-Tung Sung, Ray C. Lee
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Patent number: 6440796Abstract: A dual-gate cell structure with self-aligned gates. A polysilicon spacer forms a second gate (213) separated from a first gate (201), which is also polysilicon, by a dielectric layer (207). A drain region (219) and a source region (221) are formed next to the gates within a shallower well. The shallower well is positioned above a deep well region. In one embodiment, the second gate (213) acts as a floating gate in a flash cell. The floating gate may be programmed and erased by the application of appropriate voltage levels to the first gate (201), source (221), and/or drain (219). The self-aligned nature of the second gate (213) to the first gate (201) allows a very small dual-gate cell to be formed.Type: GrantFiled: March 30, 2001Date of Patent: August 27, 2002Assignee: Mosel Vitelic, Inc.Inventor: Kuo-Tung Sung
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Patent number: 6414350Abstract: A split gate EPROM cell and a method that includes a gate structure having a sidewall spacer of differential composition disposed about a floating gate which facilitates control of the spacer thickness during fabrication. Controlling the thickness of the spacer allows avoiding a reduction of the distance between the floating gate and the control gate as well as leakage of the charge from the floating gate.Type: GrantFiled: December 14, 1999Date of Patent: July 2, 2002Assignee: Mosel Vitelic, Inc.Inventors: Tsong-Minn Hsieh, Kuo-Tung Sung
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Patent number: 6365455Abstract: An EPROM cell and a method that includes a gate structure having a sidewall spacer. The sidewall spacer is made by way of an amorphous or polycrystalline silicon layer, which is converted into an insulating layer such as silicon dioxide. Deposition of the amorphous or polycrystalline silicon layer is more accurate and produces a more uniform layer than conventional dielectric layer deposition.Type: GrantFiled: June 5, 1998Date of Patent: April 2, 2002Assignee: Mosel Vitelic, Inc.Inventors: Wen-Doe Su, Thomas Chang, Kuo-Tung Sung, Mao Song Tseng, Shih-Chi Lai, Kun-Yu Sung, Liang-Chen Lin
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Patent number: 6352897Abstract: A method for improving an edge recess of a shallow trench isolation (STI). A SiOx layer with gap-filling ability is formed to fill the edge recess at the top corner of the STI. A part of the SiOx layer on the substrate is then removed, leaving a part of the SiOx layer to fill the edge recess and to cover a sidewall of the substrate at the edge.Type: GrantFiled: June 9, 1999Date of Patent: March 5, 2002Assignee: United Microelectronics Corp.Inventor: Kuo-Tung Sung
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Patent number: 6331721Abstract: An E2PROM or a flash memory cell having a sharp tip or thin wedge at one of its gates, e.g., the floating gate, for the erasure of electrical charges stored in the floating gate. A recess is formed between a first polysilicon gate and the substrate by removing portions of an insulating layer interposed between the first gate and the substrate. Another insulating layer, e.g., thermal oxide, is formed on the exposed portions of the first gate and the substrate, and partially fills the recess. A second polysilicon layer is formed on the thermal oxide and patterned to form a floating gate. The partially filled recess causes a sharp polysilicon tip or thin wedge to be formed as part of the floating gate. This sharp tip or thin wedge can generate a high electrical field that facilitates the removal of the stored electrical charges from the floating gate.Type: GrantFiled: March 5, 1999Date of Patent: December 18, 2001Inventors: Kuo-Tung Sung, Wen-Ting Chu, Huoy-Jong Wu
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Publication number: 20010011744Abstract: A dual-gate cell structure with self-aligned gates. A polysilicon spacer forms a second gate (213) separated from a first gate (201), which is also polysilicon, by a dielectric layer (207). A drain region (219) and a source region (221) are formed next to the gates within a shallower well. The shallower well is positioned above a deep well region. In one embodiment, the second gate (213) acts as a floating gate in a flash cell. The floating gate may be programmed and erased by the application of appropriate voltage levels to the first gate (201), source (221), and/or drain (219). The self-aligned nature of the second gate (213) to the first gate (201) allows a very small dual-gate cell to be formed.Type: ApplicationFiled: March 30, 2001Publication date: August 9, 2001Inventor: Kuo-Tung Sung
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Publication number: 20010010960Abstract: The present invention provides a novel integrated circuit device, which has a flash memory cell. The flash memory cell (100) has a tunnel dielectric layer (113) overlying a surface of a semiconductor substrate. A floating gate layer (107) is defined overlying the tunnel dielectric layer. The gate layer has an edge defined thereon, where a sidewall spacer (108) extends along and on the edge. The sidewall spacer includes a first portion defined adjacent to the edge and a second portion extending from the first portion to a region substantially outside the edge. The combination of the sidewall spacer and the gate layer provide a novel surface for increasing gate coupling ratio.Type: ApplicationFiled: March 5, 2001Publication date: August 2, 2001Inventors: A.J. Chang, Kuo-Tung Sung
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Patent number: 6265754Abstract: A capped slit provides isolation between adjacent devices of an integrated circuit. The cap and slit provide very high immunity to punchthrough and protect the edge of the slit against becoming exposed during subsequent processing that could otherwise remove field oxide. In one embodiment, the capped slit isolates two cells of a flash EEPROM device, and the field oxide lines the slit and serves as the tunneling oxide in the cells. In another embodiment, the slit is filled with a plug of dielectric material.Type: GrantFiled: October 13, 2000Date of Patent: July 24, 2001Assignee: Mosel Vitelic, Inc.Inventor: Kuo-Tung Sung
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Patent number: 6261903Abstract: The present invention provides a novel integrated circuit device, which has a flash memory cell. The flash memory cell (100) has a tunnel dielectric layer (113) overlying a surface of a semiconductor substrate. A floating gate layer (107) is defined overlying the tunnel dielectric layer. The gate layer has an edge defined thereon, where a sidewall spacer (108) extends along and on the edge. The sidewall spacer includes a first portion defined adjacent to the edge and a second portion extending from the first portion to a region substantially outside the edge. The combination of the sidewall spacer and the gate layer provide a novel surface for increasing gate coupling ratio.Type: GrantFiled: May 14, 1998Date of Patent: July 17, 2001Assignee: Mosel Vitelic, Inc.Inventors: A. J. Chang, Kuo-Tung Sung
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Patent number: 6255205Abstract: The present invention provides an EPROM and a method for forming the same having increased density. The invention does so by reducing the area required for formation of a contact. Specifically, a storage cell for an electrically programmable read-only memory having a pair of spaced-apart gate structures, with a double wall spacer structure disposed on opposite sides of each gate structure.Type: GrantFiled: June 8, 1998Date of Patent: July 3, 2001Assignee: Mosel Vitelic, Inc.Inventor: Kuo-Tung Sung
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Patent number: 6242774Abstract: A dual-gate cell structure with self-aligned gates. A polysilicon spacer forms a second gate (213) separated from a first gate (201), which is also polysilicon, by a dielectric layer (207). A drain region (219) and a source region (221) are formed next to the gates within a shallower well. The shallower well is positioned above a deep well region. In one embodiment, the second gate (213) acts as a floating gate in a flash cell. The floating gate may be programmed and erased by the application of appropriate voltage levels to the first gate (201), source (221), and/or drain (219). The self-aligned nature of the second gate (213) to the first gate (201) allows a very small dual-gate cell to be formed.Type: GrantFiled: March 11, 1999Date of Patent: June 5, 2001Assignee: Mosel Vitelic, Inc.Inventor: Kuo-Tung Sung
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Patent number: 6238977Abstract: A method for fabricating in a non-volatile memory is provided. The method includes providing a substrate having a memory region. A stacked gate structure is formed on the substrate at the memory region. A source region is formed abutting the stacked gate structure, and an isolation structure is formed to isolate the source region, in which a drain region is also formed abutting the stacked gate structure on the opposite side but not actually related to the invention. A first spacer is formed on each sidewall of the stacked gate structure. A conductive layer is form over the substrate and is patterned to remove a portion of a conductive layer. A remaining portion of the conductive layer covers the isolation structure and the source region so as to form a source line, which has an electrical coupling to each source region belong to a same word line. The stacked gate structure is therefore exposed.Type: GrantFiled: March 29, 1999Date of Patent: May 29, 2001Assignee: United Integrated Circuits CorpInventor: Kuo-Tung Sung
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Publication number: 20010001490Abstract: A semiconductor device structure with differential field oxide thicknesses. A single field oxidation step produces a nitrided field oxide region (322) that is thinner than a non-nitrided field oxide region (324). The bird's beak (326) of the nitrided field oxide (322) encroaches less into the active cell region than the bird's beak (328) of the thicker non-nitrided field oxide (324). The differential field oxide thicknesses allow isolation of multi-voltage integrated circuit devices, such as flash memory devices, while increasing available active cell area for a given design rule.Type: ApplicationFiled: December 29, 2000Publication date: May 24, 2001Inventors: Kuo-Tung Sung, Yuru Chu