Abstract: A split gate flash memory manufacturing process comprises the steps of: (a) providing a silicon substrate having a first insulating layer, and forming a first conductive layer on said first insulating layer, and forming a third insulating layer on said first conductive layer; (b) removing part of said third insulating layer and part of said first conductive layer to expose left and right sidewalls of said first conductive layer and part area of said first insulating layer; (c) performing an oxidation process to form a second insulating layer on left and right sidewalls of said first conductive layer and on said part area of said first insulating layer, wherein by a blocking function of the third insulating layer on said second insulating layer an asperity effect on left and right edges of said first conductive layer is reduced; and (d) forming a second conductive layer on said second and third insulating layers to form said split gate flash memory unit.