Abstract: Methods to improve cell performance in ROM semiconductor integrated circuit devices, in particular split gate cell flash EEPROM devices, without the need for increasing cell size or for decreasing tunnel oxide thickness. The threshold voltage under a first gate electrode (140) is adjusted using a first impurity introducing step, such as an ion implant, and the threshold voltage under a split gate electrode (170) is also adjusted using a second impurity introducing step, such as an ion implant. Depending on the type of cell used, the first gate electrode or the split gate electrode may be used as a floating gate electrode and the threshold voltage under the floating gate electrode may be adjusted separately from the other gate electrode to provide improved cell erase performance, with or without increasing the cell size or decreasing the tunnel oxide thickness.

Abstract: A dual-gate cell structure with self-aligned gates. A polysilicon spacer forms a second gate (213) separated from a first gate (201), which is also polysilicon, by a dielectric layer (207). A drain region (219) and a source region (221) are formed next to the gates. In one embodiment, the second gate (213) acts as a floating gate in a flash cell. The floating gate may be programmed and erased by the application of appropriate voltage levels to the first gate (201), source (221), and/or drain (219). The self-aligned nature of the second gate (213) to the first gate (201) allows a very small dual-gate cell to be formed.

Abstract: Improved methods for fabricating semiconductor integrated circuit devices, in particular flash EEPROM devices. According to an embodiment, the present invention provides a method of forming a semiconductor device having a gate oxide layer (120) that is thin in some regions, such as the cell region, and thicker in other regions (155), such as the periphery region. The method provides the gate oxide layer with different thicknesses without the thickness control problems of prior art methods that use contaminant-containing photoresist with an etching step. According to the present invention, the gate oxide has a first thickness that is sufficiently thin to provide high driving capability for the semiconductor device, and a second thickness that is sufficiently thick to provide high voltage reliability of the semiconductor device.

Abstract: A semiconductor device structure with differential field oxide thicknesses. A single field oxidation step produces a nitrided field oxide region (322) that is thinner than a non-nitrided field oxide region (324). The bird's beak (326) of the nitrided field oxide (322) encroaches less into the active cell region than the bird's beak (328) of the thicker non-nitrided field oxide (324). The differential field oxide thicknesses allow isolation of multi-voltage integrated circuit devices, such as flash memory devices, while increasing available active cell area for a given design rule.

Abstract: A capped slit provides isolation between adjacent devices of an integrated circuit. The cap and slit provide very high immunity to punchthrough and protect the edge of the slit against becoming exposed during subsequent processing that could otherwise remove field oxide. In one embodiment, the capped slit isolates two cells of a flash EEPROM device, and the field oxide lines the slit and serves as the tunneling oxide in the cells. In another embodiment, the slit is filled with a plug of dielectric material.

Abstract: A method and resulting integrated circuit device (100) such as a flash memory device and resulting cell. The method includes a step of providing a substrate (115), which has an active region overlying a thin layer of dielectric material (113). The method uses a step of forming a floating gate layer (107) overlying the thin layer of dielectric material (113), which is commonly termed a "tunnel oxide" layer, but is not limited to such a layer or material. The floating gate layer (107) has novel geometric features including slant edges (121), which extend to the dielectric material (123). The slant edges (121) create a smaller geometric area for the tunnel oxide region relative to the area between the floating gate layer and the control gate layer.

Abstract: A method of fabricating an interpoly dielectric layer and a gate oxide layer of a programmable memory device. This method allows a gate oxide layer and a top oxide layer of the interpoly dielectric layer to be formed simultaneously by two consecutive processes, and essentially comprises the following steps: (1) forming a bottom oxide and a nitride layer of the interpoly dielectric layer on a floating gate of the memory device; (2) defining a gate oxide growing region on the interpoly dielectric layer with a photoresist mask; (3) etching the nitride and bottom oxide layer over the area defined as the gate oxide growth region; (4) forming a first oxide layer on the gate oxide growth region and the nitride of the interpoly dielectric layer above the floating gate; and (5) forming a second oxide layer on the first oxide layer to serve simultaneously as part of the top oxide layer of the interpoly dielectric layer and as part of the gate oxide layer.

Abstract: The present invention provides novel isolation regions (501, 215) in a flash memory integrated circuit device. The isolation regions (501, 215) are formed on a silicon substrate (201), which has a core memory region (e.g., flash memory cell region) and a high voltage region (e.g., high voltage MOS device region). A silicon dioxide layer (e.g., silicon dioxide, silicon oxynitride) (203) is defined overlying the substrate including both of the regions. A nitride mask layer (205) is formed overlying the silicon dioxide layer in the core memory region and the high voltage region. This nitride mask layer exposes (207) a first isolation region coupled to the high voltage region. The first isolation region includes a first isolation structure having a first thickness of silicon dioxide. A step of oxidizing an exposed second isolation region to form the second isolation structure (215) and simultaneously oxidizing the first isolation structure to a second thickness is included.

Abstract: A method of improving junction leakage problem as STI and Salicide processes are performed is provided. The invention is to form a protective insulating layer over STI structure and the periphery of STI structure to prevent penetration of metal ions to eliminate junction leakage problem. First a silicon substrate is provided. A source/drain region and a STI structure are formed in the substrate. A sidewall recess is formed on the upper surface of the STI trench sidewall to expose the substrate. An insulating layer is formed on STI structure, the sidewall recess and the source/drain region. The insulating layer is patterned to cover STI structure and the periphery of STI structure by photolithography and etching processes. The preferred thickness of the insulating layer is thick enough to prevent penetration of metal ions formed during the Salicide process. A Salicide process is performed on the insulating layer and the conductive region.

Abstract: A method of forming self-aligned contact by using silicon spacers is provided.

Abstract: A manufacturing process of a split gate flash memory unit is disclosed. The manufacturing process includes: (a) providing a silicon substrate having a first insulating layer, and forming a first conductive layer on said first insulating layer; (b) removing part of the first conductive layer to expose left and right sidewalls of said first conductive layer and part of the first insulating layer; (c) forming a second insulating layer on left and right sidewalls of said first conductive layer; (d) performing an oxidation process to form a third insulating layer on said first conductive layer, said second insulating layer, and said other part area of said first insulating layer, wherein by an isolation effect provided by said second insulating layer a leaking phenomenon at left and right lower edges of said first conductive layer is reduced; and (e) forming a second conductive layer on said third insulating layer to form said split gate flash memory unit.

Abstract: A semiconductor integrated circuit such as a flash memory device with a novel isolation structure. Field isolation (130) is defined on a substrate (10). A spacer (107) is formed at the edges of the field isolation to protect the field isolation from oxide loss during subsequent processing steps, such as HF dips to remove polysilicon or polymer stringers that are often a part of a flash EEPROM process, for example.

Abstract: A split gate EPROM cell and a method that includes a gate structure having a sidewall spacer of differential composition disposed about a floating gate which facilitates control of the spacer thickness during fabrication. Controlling the thickness of the spacer allows avoiding a reduction of the distance between the floating gate and the control gate as well as leakage of the charge from the floating gate.

Abstract: A single-poly flash memory cell manufacturable by a standard CMOS fabrication process. A NMOS floating gate (32) is electrically connected to a PMOS floating gate (34). Both gates are fabricated in a single polysilicon process and form a flash memory cell. The floating gates are programmed by Vcc to the source (14) and drain (26) of the NMOS device (28), while applying about -Vcc to the source (20) of the PMOS device (30). Band-to-band hot electrons charge the floating gates. Biasing the NMOS device to operate as a FET allows the charge state of the gate to be sensed from the source current drawn. The memory cell is erased by applying a moderately high voltage to the source (14) NMOS device while negatively biasing the drain (22) of the PMOS device. In a particular embodiment, an integrated circuit device includes a CMOS circuit and a single-poly flash memory circuit. In a further embodiment, a DC-DC on-chip voltage converter produces the erase voltage from conventional CMOS voltage supplies.

Abstract: A novel method of fabricating a flash memory cell. The present method includes a step of providing a semiconductor substrate (101) having a first active region (111), a second active region (109), and an isolation region (103). The isolation region is defined between the first active region and second active region. The process undergoes a step of masking (105) a portion of the isolation region and the second active region, and introducing (107) a nitrogen bearing impurity by implantation into a surface of the active region. The method also includes removing the portion being masked, e.g., stripping. A step of forming a silicon oxynitride layer (117) from the nitrogen bearing impurity on the surface of the first active region and forming silicon dioxide (115) on the second active region is included.

Abstract: A method for forming a shallow trench isolation structure. A mask layer having an opening is formed over a substrate to pattern a shallow trench. A sloped spacer is formed on the sidewalls of the opening. The mask layer and the spacer are used as a hard mask, and a portion of the substrate is removed by anisotropic etching to form a shallow trench isolation structure. The sloped sidewalls of the shallow trench isolation structure and the substrate surface intersect at an obtuse angle. Therefore, the structure prevents stress and avoids leakage current.

Abstract: A method of fabricating an E.sup.2 PROM or a flash memory cell having a sharp tip or thin wedge at one of its gates, e.g., the floating gate, for the erasure of electrical charges stored in the floating gate. A recess is formed between a first polysilicon gate and the substrate by removing portions of an insulating layer interposed between the first gate and the substrate. Another insulating layer, e.g., thermal oxide, is formed on the exposed portions of the first gate and the substrate, and partially fills the recess. A second polysilicon layer is formed on the thermal oxide and patterned to form a floating gate. The partially filled recess causes a sharp polysilicon tip or thin wedge to be formed as part of the floating gate. This sharp tip or thin wedge can generate a high electrical field that facilitates the removal of the stored electrical charges from the floating gate.

Abstract: A split gate flash memory unit comprises a silicon substrate; a first insulating layer formed on said silicon substrate; a first conductive layer formed on a part area of said first insulating layer; a second insulating layer formed on left and right sidewalls of said first conductive layer and on another part area of said first insulating layer; a third insulating layer formed on said first conductive layer. The third insulating layer is also formed on said second insulating layer located at said left and right side walls of the first conductive layer in order to reduce an asperity effect on left and right edges of said first conductive layer. A second conductive layer is formed on said second and third insulating layers for being isolated from said first conductive layer by a blocking function of said second and third insulating layer.

Abstract: A process is provided for fabricating an integrated circuit in which an oxynitride layer is selectively formed in a first active region without forming an oxynitride layer in a second active region peripheral to the first active region. In one embodiment, the memory cell is fabricated where an oxynitride layer is prevented from forming in a region peripheral to the memory array region. In an alternate embodiment, the memory cell is fabricated where an oxynitride layer formed in a region peripheral to the memory array region is selectively removed.

Abstract: A method for forming a structure of a split gate flash memory is provided. The method includes steps of: a) preparing a substrate having an oxide layer; b) forming a first conducting layer over the oxide layer; c) etching a portion of the first conducting layer to form a word line structure for the flash memory; d) forming a spacer layer over the word line structure to be a side-wall portion of a word-line protecting layer; e) oxidizing the word-line protecting layer to form a dielectric layer; and f) forming a floating gate layer over the dielectric layer.