Abstract: An automatic vehicle-door activating sensing system and a method therefor are provided. The system includes: a distance sensing antenna module and an activating antenna module for generating signals; a processor generates a first distance information, a second distance information, and a activating information according to the signals. When the first distance information is less than a distance threshold and a waveform of the activating information changes, the processor generates and transmits a ready-to-activate signal to an in-vehicle system. When the second distance information is greater than the distance threshold, the processor generates and transmits a vehicle door activating signal to the in-vehicle system. The in-vehicle system can activate the vehicle door after receiving the signals in sequence. With one radar, the invention can automatically activate the vehicle door based on a user's position and kicking behavior, thereby preventing misoperation caused by detection.

Abstract: An automatic vehicle-door activating sensing system and a method therefor are provided. The system includes: a distance sensing antenna module and an activating antenna module for generating signals; a processor generates a first distance information, a second distance information, and a activating information according to the signals. When the first distance information is less than a distance threshold and a waveform of the activating information changes, the processor generates and transmits a ready-to-activate signal to an in-vehicle system. When the second distance information is greater than the distance threshold, the processor generates and transmits a vehicle door activating signal to the in-vehicle system. The in-vehicle system can activate the vehicle door after receiving the signals in sequence. With one radar, the invention can automatically activate the vehicle door based on a user's position and kicking behavior, thereby preventing misoperation caused by detection.

Abstract: A heat conducting module includes a main body. The main body includes a first surface and a second surface. The first surface is thermally connected to a heat absorbing body. The second surface is opposite to the first surface and is fluidly connected to a channel. The second surface has a plurality of grooves disposed along a direction. The channel allows a fluid to flow a long the direction. Each of the grooves includes a first sub-groove and at least one second sub-groove. The first sub-groove at least has a third surface close to the first surface. The first sub-groove at least partially communicates with the second sub-groove, and the second sub-groove is at least partially fluidly connected with the third surface.

Abstract: A heat conducting module includes a main body. The main body includes a first surface and a second surface. The first surface is thermally connected to a heat absorbing body. The second surface is opposite to the first surface and is fluidly connected to a channel. The second surface has a plurality of grooves disposed along a direction. The channel allows a fluid to flow a long the direction. Each of the grooves includes a first sub-groove and at least one second sub-groove. The first sub-groove at least has a third surface close to the first surface. The first sub-groove at least partially communicates with the second sub-groove, and the second sub-groove is at least partially fluidly connected with the third surface.

Abstract: A method of fabricating a heat exchanger unit is provided. The method includes forming a first heat exchange component by providing a first inlet interface device; providing a first outlet interface device; providing a first set of pipes; and connecting respective first ends of each of the first set of pipes to the first inlet interface device and connecting a respective second ends of the each of the first set of pipes to the first outlet interface device. The method further includes forming a second heat exchange component in the same fashion as the first heat exchange component. The method also includes overlapping the first and second heat exchange components and cross-coupling the first set of pipes and the second set of pipes at a plurality of joints.

Abstract: A method to realize IP flow mobility (IFOM) between 3GPP access and non-3GPP access over GTP based interfaces is proposed. A user equipment is connected to a PDN-GW via a 3GPP access network and a non-3GPP access network. The UE transmits an IFOM triggering message to the PDN-GW, which selects IP flows to be moved based on EPS bearer ID and IP flow description. The PDN-GW sends an Update Bearer Request to a WAG or ePDG, and updates its mapping table if the Update Bearer Request is successful. The UE also updates its mapping table upon receiving an IFOM acknowledgement from the WAG or ePDG. The PDN-GW initiates a 3GPP bearer modification procedure to move the selected IP flows.

Abstract: Disclosed herein are intermediate and solder bump structures. In one embodiment, a structure comprises a primary solder column comprising primary solder material and configured to electrically contact a bonding pad on a semiconductor substrate. The structure also comprises at least one secondary solder column comprising secondary solder material in electrical contact with the primary solder column, the at least one secondary column having a height and volume less than a height and volume of the primary solder column. In such structures, the primary solder column is further configured to form a primary solder bump comprising the primary solder material and at least a portion of the secondary solder material through cohesion from the at least one secondary solder column when the intermediate structure undergoes a reflow process.

Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.

Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.

Abstract: A method of GPS bit synchronization is disclosed. The method includes the steps of a) receiving plural serial C/A Codes, wherein a data bit is formed by m C/A Codes; b) sequentially providing a bin number ranged from 0 to m?1 to the plural C/A Codes; c) setting a sampling value k; d) sequentially determining adjacent two C/A Codes, C/A Code nk and C/A Code (n+1)k, wherein n={0, 1, 2, 3, . . . }, and calculating a sign change aggregate value of each bin number ranged from 0 to m?1; e) repeating step d) till there are k bin numbers having the sign change aggregate value equal to or greater than a first threshold, and summing the k bin numbers for obtaining a lookup value; and f) acquiring a bit boundary of the data bit according to the lookup value in the plural serial C/A Codes.

Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.

Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.

Abstract: The present invention discloses a fluidic mixer of serpentine channel incorporated with staggered sudden-expansion and convergent cross sections, which comprises a flat cover and a channel body. The channel body further comprises two L-type mixer inlets, a mixing channel, and two L-type mixer outlets. The configuration of the mixing channel is a single serpentine channel incorporated with staggered sudden-expansion and convergent cross sections, wherein the serpentine structure and the sudden-expansion cross sections induces split flows, which further enable the fluid to stretch and fold so that the contact area within the fluid can be increased. The convergence after sudden expansion in cross section is to prepare the next action of sudden expansion, and such an iterative structure can obviously enhance the mixing effect.

Abstract: It is an object of the present invention to provide a method for solder bump formation using a combination of eutectic and high lead solders. The present invention provides a method for improving a solder bump composition for a flip chip.

Abstract: Disclosed herein are intermediate and solder bump structures. In one embodiment, a structure comprises a primary solder column comprising primary solder material and configured to electrically contact a bonding pad on a semiconductor substrate. The structure also comprises at least one secondary solder column comprising secondary solder material in electrical contact with the primary solder column, the at least one secondary column having a height and volume less than a height and volume of the primary solder column. In such structures, the primary solder column is further configured to form a primary solder bump comprising the primary solder material and at least a portion of the secondary solder material through cohesion from the at least one secondary solder column when the intermediate structure undergoes a reflow process.

Abstract: It is an object of the present invention to provide a method for solder bump formation using a combination of eutectic and high lead solders. The present invention provides a method for improving a solder bump composition for a flip chip.

Abstract: A novel under-bump metallization (UBM) structure for providing electrical communication is described. The UBM structure includes a plurality of metallic layers, which are deposited onto a bonding pad of a semiconductor device, such as a semiconductor chip. The UBM structure may be provided as an interface between the bonding pad and a solder bump deposited over the UBM structure. In one example, the UBM structure includes layers of nickel and copper in which nickel is the upper layer in contact with the solder bump and copper is the lower layer in contact with the bonding pad. The nickel layer is formed to include a downwardly depending perimeter portion, which serves as a cover to the copper layer of the UBM structure. Accordingly, the copper layer is shielded from contact with the solder material during the reflow process, thereby avoiding undesirable reactions between the copper and solder.

Abstract: A method for preventing lead precipitation during wafer processing is disclosed. The method includes singulating a semiconductor wafer having a plurality of solder bumps and applying cold deionized (DI) water to the semiconductor wafer during singulation. Application of the cold DI water reduces or prevents lead precipitation during the singulation process, and thereby reduces the presence of bump oxidation.

Abstract: Disclosed herein are a method of manufacturing a solder bump on a semiconductor device, a solder bump structure formed on a substrate, and an intermediate solder bump structure. In one embodiment, the method includes creating a bonding pad over a semiconductor substrate, and placing a mask layer over the substrate and the bonding pad. The method also includes forming an opening in the mask layer having a primary solder mold and at least one secondary solder mold joined with the primary mold, where the opening exposes a portion of the bonding pad. In this embodiment, the method further includes filling the primary solder mold and the at least one secondary solder mold with solder material to form corresponding primary and at least one secondary solder columns in electrical contact with the bonding pad. The method also includes removing the mask layer after the filling of the solder molds with the solder material.

Abstract: An IC chip heat sink and method for dissipating heat from an integrated circuit (IC) chip, is disclosed. In a typical embodiment, the IC chip heat sink is fabricated by depositing a metal seed layer on the backside of a semiconductor wafer having multiple IC chips fabricated thereon. A photoresist layer is then deposited on the seed layer and patterned to define multiple photoresist openings. Multiple columns are formed on the seed layer by the electrochemical plating of a metal in the photoresist openings. Finally, the photoresist is stripped from the seed layer to define the multiple columns, which extend from the seed layer, and a network of heat sink channels between the columns. During functioning of the chip, heat is dissipated from the chip through the heat sink.