Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.

Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.

Abstract: A method of GPS bit synchronization is disclosed. The method includes the steps of a) receiving plural serial C/A Codes, wherein a data bit is formed by m C/A Codes; b) sequentially providing a bin number ranged from 0 to m?1 to the plural C/A Codes; c) setting a sampling value k; d) sequentially determining adjacent two C/A Codes, C/A Code nk and C/A Code (n+1)k, wherein n={0, 1, 2, 3, . . . }, and calculating a sign change aggregate value of each bin number ranged from 0 to m?1; e) repeating step d) till there are k bin numbers having the sign change aggregate value equal to or greater than a first threshold, and summing the k bin numbers for obtaining a lookup value; and f) acquiring a bit boundary of the data bit according to the lookup value in the plural serial C/A Codes.

Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.

Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.

Abstract: The present invention discloses a fluidic mixer of serpentine channel incorporated with staggered sudden-expansion and convergent cross sections, which comprises a flat cover and a channel body. The channel body further comprises two L-type mixer inlets, a mixing channel, and two L-type mixer outlets. The configuration of the mixing channel is a single serpentine channel incorporated with staggered sudden-expansion and convergent cross sections, wherein the serpentine structure and the sudden-expansion cross sections induces split flows, which further enable the fluid to stretch and fold so that the contact area within the fluid can be increased. The convergence after sudden expansion in cross section is to prepare the next action of sudden expansion, and such an iterative structure can obviously enhance the mixing effect.

Abstract: It is an object of the present invention to provide a method for solder bump formation using a combination of eutectic and high lead solders. The present invention provides a method for improving a solder bump composition for a flip chip.

Abstract: Disclosed herein are intermediate and solder bump structures. In one embodiment, a structure comprises a primary solder column comprising primary solder material and configured to electrically contact a bonding pad on a semiconductor substrate. The structure also comprises at least one secondary solder column comprising secondary solder material in electrical contact with the primary solder column, the at least one secondary column having a height and volume less than a height and volume of the primary solder column. In such structures, the primary solder column is further configured to form a primary solder bump comprising the primary solder material and at least a portion of the secondary solder material through cohesion from the at least one secondary solder column when the intermediate structure undergoes a reflow process.

Abstract: It is an object of the present invention to provide a method for solder bump formation using a combination of eutectic and high lead solders. The present invention provides a method for improving a solder bump composition for a flip chip.

Abstract: A novel under-bump metallization (UBM) structure for providing electrical communication is described. The UBM structure includes a plurality of metallic layers, which are deposited onto a bonding pad of a semiconductor device, such as a semiconductor chip. The UBM structure may be provided as an interface between the bonding pad and a solder bump deposited over the UBM structure. In one example, the UBM structure includes layers of nickel and copper in which nickel is the upper layer in contact with the solder bump and copper is the lower layer in contact with the bonding pad. The nickel layer is formed to include a downwardly depending perimeter portion, which serves as a cover to the copper layer of the UBM structure. Accordingly, the copper layer is shielded from contact with the solder material during the reflow process, thereby avoiding undesirable reactions between the copper and solder.

Abstract: A method for preventing lead precipitation during wafer processing is disclosed. The method includes singulating a semiconductor wafer having a plurality of solder bumps and applying cold deionized (DI) water to the semiconductor wafer during singulation. Application of the cold DI water reduces or prevents lead precipitation during the singulation process, and thereby reduces the presence of bump oxidation.

Abstract: Disclosed herein are a method of manufacturing a solder bump on a semiconductor device, a solder bump structure formed on a substrate, and an intermediate solder bump structure. In one embodiment, the method includes creating a bonding pad over a semiconductor substrate, and placing a mask layer over the substrate and the bonding pad. The method also includes forming an opening in the mask layer having a primary solder mold and at least one secondary solder mold joined with the primary mold, where the opening exposes a portion of the bonding pad. In this embodiment, the method further includes filling the primary solder mold and the at least one secondary solder mold with solder material to form corresponding primary and at least one secondary solder columns in electrical contact with the bonding pad. The method also includes removing the mask layer after the filling of the solder molds with the solder material.

Abstract: An IC chip heat sink and method for dissipating heat from an integrated circuit (IC) chip, is disclosed. In a typical embodiment, the IC chip heat sink is fabricated by depositing a metal seed layer on the backside of a semiconductor wafer having multiple IC chips fabricated thereon. A photoresist layer is then deposited on the seed layer and patterned to define multiple photoresist openings. Multiple columns are formed on the seed layer by the electrochemical plating of a metal in the photoresist openings. Finally, the photoresist is stripped from the seed layer to define the multiple columns, which extend from the seed layer, and a network of heat sink channels between the columns. During functioning of the chip, heat is dissipated from the chip through the heat sink.

Abstract: A new method and processing sequence is provided for the formation of solder bumps that are in contact with underlying aluminum contact pads. A patterned layer of negative photoresist is interposed between a patterned layer of PE Si3N4 and a patterned layer of polyamide insulator. The patterned negative photoresist partially overlays the aluminum contact pad and prevents contact between the layer of polyamide insulator and the aluminum contact pad. By forming this barrier no moisture that is contained in the polyamide insulator can come in contact with the aluminum contact pad, therefore no corrosion in the surface of the aluminum contact pad can occur.

Abstract: A new process is provided which is an extension and improvement of present processing for the creation of a solder bump. After the layers of Under Bump Metal and a layer of solder metal have been created in patterned and etched format and overlying the contact pad, following a conventional processing sequence, a layer of polyimide is deposited. The solder flow is performed using the thickness of the deposited layer of polyimide to control the height of the column underneath the reflown solder.

Abstract: A new method and processing sequence is provided for the creation of interconnect bumps. A layer of passivation is deposited over a contact pad and patterned, creating an opening in the layer of passivation that aligns with the contact pad. A layer of UBM metal is deposited over the layer of passivation, the layer of UBM is overlying the contact pad and limited to the immediate surroundings of the contact pad. The central surface of the layer of UBM is selectively electroplated after which a layer of solder or solder alloy is solder printed over the electroplated surface of the layer of UBM. A solder flux or paste is applied over the surface of the solder printed solder compound or solder alloy. Flowing of the solder or solder alloy creates the solder bump of the invention.

Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.

Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.

Abstract: A wafer bumping method comprising the following steps of. A wafer having fields is provided. The wafer having at least one wafer identification character formed thereon within one or more of the fields. A dry film resist is formed over the wafer. Portions of the dry film resist are selectively exposed field by field using a mask whereby the mask is shifted over the one or more fields containing the at least one wafer identification character so that the one or more fields containing the at least one wafer identification character is double exposed after the mask shift so that all of the one or more fields containing the at least one wafer identification character is completely exposed. The selectively exposed dry film resist is developed to remove the non-exposed portions of the dry film resist.

Abstract: A method of making electrically conductive bumps of improved height on a semiconductor device. The method includes steps of depositing an under bump metallurgy over a semiconductor device onto a contact pad; depositing and patterning a photoresist layer to provide an opening over the under bump metallurgy; depositing a first electrically conductive material into the opening in the photoresist layer; depositing a second electrically conductive material over the first electrically conductive material; removing the photoresist layer and the excess under bump metallurgy; applying a flux agent to the top surface of the second electrically conductive material; hard baking the semiconductor device to remove any oxide; dipping a portion of the semiconductor device in an electroless plating solution; removing the semiconductor device from the electroless plating solution; and reflowing the electrically conductive materials to provide a bump of improved height on the semiconductor device.