Patents by Inventor Kuo-Wei Lin
Kuo-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040005771Abstract: A new process is provided which is an extension and improvement of present processing for the creation of a solder bump. After the layers of Under Bump Metal and a layer of solder metal have been created in patterned and etched format and overlying the contact pad, following a conventional processing sequence, a layer of polyimide is deposited. The solder flow is performed using the thickness of the deposited layer of polyimide to control the height of the column underneath the reflown solder.Type: ApplicationFiled: July 3, 2003Publication date: January 8, 2004Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Yang-Tung Fan, Cheng-Yu Chu, Fu-Jier Fan, Shih-Jane Lin, Chiou-Shian Peng, Yen-Ming Chen, Kuo-Wei Lin
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Patent number: 6649507Abstract: A method of forming a bump structure, comprising the following steps. A structure having an exposed first conductive structure is provided. A first photoresist layer is formed over the structure and the exposed first conductive structure. A second capping photoresist layer is formed over the first photoresist layer. The first and second photoresist layers being comprised of different photoresist materials. The first and second photoresist layers are patterned to form an opening through the first and second photoresist layers and over the first conductive structure. The second capping photoresist layer prevents excessive formation of first photoresist layer residue during processing. A second conductive structure is formed within the opening. The first and second patterned photoresist layers are stripped. The second conductive structure is reflowed to form the bump structure.Type: GrantFiled: June 18, 2001Date of Patent: November 18, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yen-Ming Chen, Cheng-Yu Chu, Kuo-Wei Lin, Chiou-Shian Peng, Yang-Tung Fan, Fu-Jier Fan, Shih-Jane Lin
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Publication number: 20030199159Abstract: A new method and processing sequence is provided for the formation of solder bumps that are in contact with underlying aluminum contact pads. A patterned layer of negative photoresist is interposed between a patterned layer of PE Si3N4 and a patterned layer of polyamide insulator. The patterned negative photoresist partially overlays the aluminum contact pad and prevents contact between the layer of polyamide insulator and the aluminum contact pad. By forming this barrier no moisture that is contained in the polyamide insulator can come in contact with the aluminum contact pad, therefore no corrosion in the surface of the aluminum contact pad can occur.Type: ApplicationFiled: May 13, 2003Publication date: October 23, 2003Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Fu-Jier Fan, Cheng-Yu Chu, Kuo Wei Lin, Shih-Jang Lin, Yang-Tung Fran, Chiou-Shian Peng
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Patent number: 6632700Abstract: A new method to form color image sensor cells without damaging bonding pads in the manufacture of an integrated circuit device is achieved. The method comprises, first, forming cell electrodes and bonding pads on a semiconductor substrate. A passivation layer is formed overlying the cell electrodes but exposing the top surface of the bonding pads. The semiconductor substrate is then dipped in a hydrogen peroxide solution to thereby form a metal oxide layer overlying the bonding pads. A first transparent planarization layer is deposited overlying the passivation layer and the metal oxide layer. A color filter photoresist layer is deposited overlying the first transparent planarization layer. The color filter photoresist layer is patterned to form color filter elements to complete the color image sensor cells in the manufacture of the integrated circuit device. The presence of the metal oxide layer prevents damage to the bonding pads from an alkaline developer.Type: GrantFiled: April 30, 2002Date of Patent: October 14, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yang-Tung Fan, Cheng-Yu Chu, Chiou-Shian Peng, Shih-Jane Lin, Yen-Ming Chen, Fu-Jier Fan, Kuo-Wei Lin
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Patent number: 6605524Abstract: A new process is provided which is an extension and improvement of present processing for the creation of a solder bump. After the layers of Under Bump Metal and a layer of solder metal have been created in patterned and etched format and overlying the contact pad, following a conventional processing sequence, a layer of polyimide is deposited. The solder flow is performed using the thickness of the deposited layer of polyimide to control the height of the column underneath the reflown solder.Type: GrantFiled: September 10, 2001Date of Patent: August 12, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yang-Tung Fan, Cheng-Yu Chu, Fu-Jier Fan, Shih-Jane Lin, Chiou-Shian Peng, Yen-Ming Chen, Kuo-Wei Lin
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Publication number: 20030124763Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.Type: ApplicationFiled: October 16, 2002Publication date: July 3, 2003Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Yang-Tung Fan, Chiou-Shian Peng, Cheng-Yu Chu, Shih-Jane Lin, Yen-Ming Chen, Fu-Jier Fan, Kuo-Wei Lin
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Patent number: 6586323Abstract: A new method and processing sequence is provided for the formation of solder bumps that are in contact with underlying aluminum contact pads. A patterned layer of negative photoresist is interposed between a patterned layer of PE Si3N4 and a patterned layer of polyamide insulator. The patterned negative photoresist partially overlays the aluminum contact pad and prevents contact between the layer of polyamide insulator and the aluminum contact pad. By forming this barrier no moisture that is contained in the polyamide insulator can come in contact with the aluminum contact pad, therefore no corrosion in the surface of the aluminum contact pad can occur.Type: GrantFiled: September 18, 2000Date of Patent: July 1, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Fu-Jier Fan, Cheng-Yu Chu, Kuo Wei Lin, Shih-Jang Lin, Yang-Tung Fan, Chiou-Shian Peng
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Patent number: 6583039Abstract: A method of forming a bump overlying the copper based contact pad to prevent oxidation of the copper based contact pad. A passivation blanket is deposited over a semiconductor device having a copper based contact pad, the passivation blanket includes a first layer overlying the top surface; a second layer overlying the first layer; a portion of the second layer overlying the copper based contact pad is removed leaving the first layer in place; depositing an under bump metallurgy over the semiconductor device, a portion of the first layer overlying the copper based contact pad is removed so that the copper based contact pad has limited exposure to oxygen; depositing an under bump metallurgy over the semiconductor device; removing excess under bump metallurgy; depositing an electrically conductive material over the under bump metallurgy; reflowing electrically conductive material to form a bump overlying the copper based contact pad.Type: GrantFiled: October 15, 2001Date of Patent: June 24, 2003Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Ming Chen, Kuo-Wei Lin, Cheng-Yu Chu, Yang-Tung Fan, Fu-Jier Fan, Shih-Jane Lin, Chiou-Shian Peng, Hsien-Tsung Liu
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Publication number: 20030073036Abstract: A method of making electrically conductive bumps of improved height on a semiconductor device. The method includes steps of depositing an under bump metallurgy over a semiconductor device onto a contact pad; depositing and patterning a photoresist layer to provide an opening over the under bump metallurgy; depositing a first electrically conductive material into the opening in the photoresist layer; depositing a second electrically conductive material over the first electrically conductive material; removing the photoresist layer and the excess under bump metallurgy; applying a flux agent to the top surface of the second electrically conductive material; hard baking the semiconductor device to remove any oxide; dipping a portion of the semiconductor device in an electroless plating solution; removing the semiconductor device from the electroless plating solution; and reflowing the electrically conductive materials to provide a bump of improved height on the semiconductor device.Type: ApplicationFiled: October 12, 2001Publication date: April 17, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chiou-Shian Peng, Euegene Chu, Alex Fahn, Kenneth Lin, Gilbert Fane, James Chen, Kuo-Wei Lin
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Publication number: 20030073300Abstract: A method of forming a bump overlying the copper based contact pad to prevent oxidation of the copper based contact pad. A passivation blanket is deposited over a semiconductor device having a copper based contact pad, the passivation blanket includes a first layer overlying the top surface; a second layer overlying the first layer; a portion of the second layer overlying the copper based contact pad is removed leaving the first layer in place; depositing an under bump metallurgy over the semiconductor device, a portion of the first layer overlying the copper based contact pad is removed so that the copper based contact pad has limited exposure to oxygen; depositing an under bump metallurgy over the semiconductor device; removing excess under bump metallurgy; depositing an electrically conductive material over the under bump metallurgy; reflowing electrically conductive material to form a bump overlying the copper based contact pad.Type: ApplicationFiled: October 15, 2001Publication date: April 17, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Ming Chen, Kuo-Wei Lin, Cheng-Yu Chu, Yang-Tung Fan, Fu-Jier Fan, Shih-Jane Lin, Chiou-Shian Peng, Hsien-Tsung Liu
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Patent number: 6534396Abstract: Within a method for forming a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a patterned conductor layer having a topographic variation at a periphery of the patterned conductor layer. There is then formed over the substrate and passivating the topographic variation at the periphery of the patterned conductor layer a planarizing passivation layer formed of a thermally reflowable material. There is then formed upon the planarizing passivation layer a dimensionally stabilizing layer. Finally, there is then thermally annealed the microelectronic fabrication to form from the planarizing passivation layer a thermally annealed planarizing passivation layer. By employing formed upon the planarizing passivation layer the dimensionally stabilizing layer, there is attenuated within the thermally annealed planarizing passivation layer replication of the topographic variation at the periphery of the patterned conductor layer.Type: GrantFiled: October 10, 2000Date of Patent: March 18, 2003Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-Jier Fahn, Kuo-Wei Lin, James Chen, Eugene Cheu, Chien-Shian Peng, Gilbert Fan, Kenneth Lin
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Patent number: 6482669Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.Type: GrantFiled: May 30, 2001Date of Patent: November 19, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yang-Tung Fan, Chiou-Shian Peng, Cheng-Yu Chu, Shih-Jane Lin, Yen-Ming Chen, Fu-Jier Fan, Kuo-Wei Lin
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Publication number: 20020127836Abstract: A new method and processing sequence is provided for the creation of interconnect bumps. A layer of passivation is deposited over a contact pad and patterned, creating an opening in the layer of passivation that aligns with the contact pad. A layer of UBM metal is deposited over the layer of passivation, the layer of UBM is overlying the contact pad and limited to the immediate surroundings of the contact pad. The central surface of the layer of UBM is selectively electroplated after which a layer of solder or solder alloy is solder printed over the electroplated surface of the layer of UBM. A solder flux or paste is applied over the surface of the solder printed solder compound or solder alloy. Flowing of the solder or solder alloy creates the solder bump of the invention.Type: ApplicationFiled: May 16, 2002Publication date: September 12, 2002Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Kuo-Wei Lin, Cheng-Yu Chu, Yen-Ming Chen, Yang-Tung Fan, Fu-Jier Fan, Chiou Shian Peng, Shih-Jang Lin
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Patent number: 6426283Abstract: A method for bumping and backlapping a semiconductor wafer that has a multiplicity of solder bumps formed on an active surface of the wafer is disclosed. In the method, a preprocessed wafer that has a multiplicity of bond pads formed on a top surface is first provided, a under-bump-metallurgy (UBM) layer is then sputter deposited on top of the wafer surface, followed by the lamination of a dry film resist layer on top of the UBM layer. The dry film resist layer is then patterned with a multiplicity of openings exposing the multiplicity of bond pads, followed by the deposition of a solder material into the multiplicity of openings to form the solder bump's. A protective tape is then adhesively bonded to the top of the dry film resist layer before the wafer is positioned into a backlapping apparatus for removing of a preselected thickness from the backside of the wafer.Type: GrantFiled: December 1, 2000Date of Patent: July 30, 2002Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Yen-Ming Chen, Kuo-Wei Lin, Cheng-Yu Chu, Fu-Jier Fan, Yang-Tung Fan, Chiou-Shian Peng, Shih-Jane Lin
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Patent number: 6426281Abstract: A new method and processing sequence is provided for the creation of interconnect bumps. A layer of passivation is deposited over a contact pad and patterned, creating an opening in the layer of passivation that aligns with the contact pad. A layer of UBM metal is deposited over the layer of passivation, the layer of UBM is overlying the contact pad and limited to the immediate surroundings of the contact pad. The central surface of the layer of UBM is selectively electroplated after which a layer of solder or solder alloy is solder printed over the electroplated surface of the layer of UBM. A solder flux or paste is applied over the surface of the solder printed solder compound or solder alloy. Flowing of the solder or solder alloy creates the solder bump of the invention.Type: GrantFiled: January 16, 2001Date of Patent: July 30, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Kuo-Wei Lin, Cheng-Yu Chu, Yen-Ming Chen, Yang-Tung Fan, Fu-Jier Fan, Chiou-Shian Peng, Shih-Jang Lin
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Publication number: 20020068425Abstract: A method for bumping and backlapping a semiconductor wafer that has a multiplicity of solder bumps formed on an active surface of the wafer is disclosed. In the method, a preprocessed wafer that has a multiplicity of bond pads formed on a top surface is first provided, a under-bump-metallurgy (UBM) layer is then sputter deposited on top of the wafer surface, followed by the lamination of a dry film resist layer on top of the UBM layer. The dry film resist layer is then patterned with a multiplicity of openings exposing the multiplicity of bond pads, followed by the deposition of a solder material into the multiplicity of openings to form the solder bumps. A protective tape is then adhesively bonded to the top of the dry film resist layer before the wafer is positioned into a backlapping apparatus for removing of a preselected thickness from the backside of the wafer.Type: ApplicationFiled: December 1, 2000Publication date: June 6, 2002Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Yen-Ming Chen, Kuo-Wei Lin, Cheng-Yu Chu, Fu-Jier Fan, Yang-Tung Fan, Chiou-Shian Peng, Shin Chen Lin
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Patent number: 6372545Abstract: A method for forming an under bump metal, comprising the following steps. A semiconductor structure is provided having an exposed I/O pad. A patterned passivation layer is formed over the semiconductor structure, the patterned passivation layer having an opening exposing a first portion of the I/O pad. A dry film resistor (DFR) layer is laminated, exposed and developed to form a patterned dry film resistor (DFR) layer over the patterned passivation layer. The patterned dry film resistor (DFR) layer having an opening exposing a second portion of the I/O pad. The patterned dry film resistor (DFR) layer opening having opposing side walls with a predetermined profile with an undercut. A metal layer is formed over the patterned dry film resistor (DFR) layer, the exposed third portion of the I/O pad, and over at least a portion of the opposing side walls of the patterned dry film resistor (DFR) layer opening.Type: GrantFiled: March 22, 2001Date of Patent: April 16, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Fu-Jier Fan, Kuo-Wei Lin, Yen-Ming Chen, Cheng-Yu Chu, Shih-Jane Lin, Chiou-Shian Peng, Yang-Tung Fan
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Patent number: 6319846Abstract: A method for removing a multiplicity of solder bodies connected to a semiconductor wafer through a copper wetting layer from the semiconductor wafer is disclosed. In the method, a semiconductor wafer that has on a top surface a multiplicity of solder bodies electrically connected to a multiplicity of bond pads through a multiplicity of copper wetting layers is first provided. When the multiplicity of solder bodies is found out of specification or must be removed for any other quality reasons, the semiconductor wafer is exposed to an etchant that has an etch rate toward the copper wetting layer at least 5 times the etch rate toward a metal that forms the multiplicity of bond pads. The semiconductor wafer may be removed from the etchant when the multiplicity of copper wetting layers is substantially dissolved such that the multiplicity of solder bodies is separated from the multiplicity of bond pads. The multiplicity of solder bodies may be either solder bumps or solder balls.Type: GrantFiled: January 5, 2001Date of Patent: November 20, 2001Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Kuo-Wei Lin, James Chen, Eugene Chu, Alex Fahn, Chiou-Shian Peng, Gilbert Fane, Kenneth Lin