Abstract: A plurality of photovoltaic junctions for a subpixel may be formed in a semiconductor substrate. After thinning the backside of the semiconductor substrate, at least one transparent refraction structure may be formed on the backside surface of the thinned semiconductor substrate. Each transparent refraction structure has a variable thickness that decreases with a lateral distance from a vertical axis passing through a geometrical center of the second-conductivity-type pillar structures for the subpixel. A subpixel optics assembly including an optical lens may be formed over the at least one transparent refraction structure. Each transparent refraction structure may reduce the tilt angle of light that propagate downward into the photodetectors, and increases total internal reflection of light and increase the efficiency of the photodetectors.

Abstract: A semiconductor device, a back-side deep trench isolation (BDTI) structure of a semiconductor device, and method of manufacturing a semiconductor structure are provided. The semiconductor device, comprising: a pixel region disposed within a substrate and comprising an image sensing element configured to convert electromagnetic radiation into an electrical signal; and one or more BDTI structures extending from a first-side of the substrate to positions within the substrate; wherein the one or more of BDTI structures comprise one or more ferroelectric materials.

Abstract: A thin film transistor includes a bottom gate, a semiconductor layer, a top gate, a first auxiliary conductive pattern, a source, and a drain. The semiconductor layer includes a first semiconductor region, a second semiconductor region, a first heavily doped region, a second heavily doped region, a third heavily doped region, a first lightly doped region, a second lightly doped region, and a third lightly doped region. The first heavily doped region and the second heavily doped region are respectively located on two sides of the first semiconductor region. Two ends of the second semiconductor region are directly connected to the third heavily doped region and the third lightly doped region, respectively. The top gate is electrically connected to the bottom gate. The source and the drain are respectively electrically connected to the third heavily doped region and the second heavily doped region of the semiconductor layer.

Abstract: A method of operating a memory cell includes the following steps. A first plurality of bias operations is performed to the memory cell using a first voltage, wherein the memory cell comprises a variable resistance pattern, and the first voltage of each cycle of the first plurality of bias operations has a same first polarity. The memory cell is determined whether reaches a fatigue threshold. After the determination determines that the memory cell reaches the fatigue threshold, a second plurality of bias operations is performed to the memory cell using a second voltage, wherein the second voltage of each cycle of the second plurality of bias operations has a same second polarity, and the second polarity is opposite to the first polarity.

Abstract: A portable coating device for applying a coating solution onto a solar panel includes a supply module for supplying the coating solution, a base, a spraying module disposed on the base, a transmission module disposed at two opposite ends of the base, an arc bracket, and an applicator. The base spans the solar panel and moves thereon through the support of the transmission module. The arc bracket is disposed at the bottom of the base and has a plurality of seepage openings, and an inner surface of the arc bracket faces the spraying module. The applicator includes a porous material that deforms under pressure. The applicator is assembled to the base and supported by the arc bracket.

Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a buffer layer on the substrate, forming a mesa isolation on the HEMT region, forming a HEMT on the mesa isolation, and then forming a capacitor on the capacitor region. Preferably, a bottom electrode of the capacitor contacts the buffer layer directly.

Abstract: An optical image capturing system, along an optical axis from an object side to an image side, includes a lens and an optical filter. The lens has refractive power. The optical filter is adjacent to the lens. The lens and/or the optical filter include or includes at least one visible light absorbing ingredient, absorb or absorbs a visible light with a wavelength range from 400 nm to 700 nm, and allows a light with a wavelength range greater than 800 nm to pass correspondingly. In another embodiment, a plurality of lenses is provided. At least one of the lenses is a filter lens. The filter lens includes the at least one visible light absorbing ingredient, so that the optical image capturing system could absorb the visible light and has a high transmittance of the infrared, thereby improving a light receiving efficiency and a working quality.

Abstract: A biochip includes a substrate, an insulating layer, a semiconductor layer, a dielectric layer, a metal layer, and a protective layer. The semiconductor layer is disposed on the insulating layer and has a reaction region. The dielectric layer is disposed on the semiconductor layer and has a first opening. The metal layer is disposed on the dielectric layer and includes a source, a drain, and a wall structure. The wall structure surrounds the first opening, the source, and the drain. The protective layer is disposed on the metal layer and has a flat part, a protruding part, a second opening, and a third opening. The flat part surrounds and defines the second opening. The protruding part is disposed corresponding to the wall structure, and the protruding part surrounds and defines the third opening. The second opening connects the third opening and the first opening to expose the reaction region.

Abstract: A memory device includes multiple first memory cells each having a first terminal coupled to a first node and a second terminal coupled to a corresponding one in multiple first bit lines; multiple second memory cells each having a first terminal coupled to a second node and a second terminal coupled to a corresponding one in multiple second bit lines; and a driver circuit coupled between the first node and the second node, and configured to generate, in response to a first voltage at the first node, a second voltage at the second node when a memory operation is performed to one of the first memory cells. The first voltage and the second voltage have different polarity.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a buffer layer on the substrate, forming a mesa isolation on the HEMT region, forming a HEMT on the mesa isolation, and then forming a capacitor on the capacitor region. Preferably, a bottom electrode of the capacitor contacts the buffer layer directly.

Abstract: The present invention provides a light emitting panel, which includes: a substrate, at least one light emitting element disposed on the substrate, and a reflective structure layer. The reflective structure layer includes a plurality of first microstructure units disposed on the substrate and distributed around the at least one light emitting element, and a plurality of second microstructure units disposed on and overlapping the first microstructure units. A spacing between adjacent first microstructure units among the first microstructure units is less than a spacing between adjacent second microstructure units among the second microstructure units.

Abstract: A signal filter includes a notch filter and a wideband filter. The notch filter is configured to perform a band-rejection filtering operation according to a band-rejection filtering property. The wideband filter is coupled to the notch filter, and is configured to perform a wideband filtering operation according to a wideband filtering property. The band-rejection filtering property includes a first cutoff frequency, a frequency bandwidth, a relatively high quality factor and a relatively low coupling coefficient. The wideband filtering property includes a second cutoff frequency, a relatively low quality factor and a relatively high coupling coefficient. The first and the second cutoff frequencies have a frequency difference therebetween. A ratio of the frequency difference to the frequency bandwidth is within a preset ratio range being from 2.5% to 20%.

Abstract: A display device includes a substrate, a transistor, a first conductive feature, a conductive pad and a light-emitting device. The substrate has a first area. The transistor is located in the first area. The first conductive feature is located over the transistor and electrically connects a source/drain of the transistor. The first conductive feature includes a first protective layer and a first conductive layer. The first protective layer has a first thickness and at least includes titanium. The first conductive layer is located above the first protective layer, has a second thickness and includes aluminum. The second thickness is greater than the first thickness. The conductive pad is located on the first conductive feature and electrically connects the first conductive feature. The conductive pad at least includes nickel and gold. The light-emitting device is located on the conductive pad and electrically connects the conductive pad.

Abstract: An integrated circuit includes a first circuit, a comparator, a counter and a control circuit. The first circuit is configured to generate a ramp reference signal. The comparator is configured generate a comparator output signal in response to comparing a pixel output signal and the ramp reference signal. The counter is coupled to the comparator, and configured to be turned on or turned off in response to the comparator output signal. The control circuit is coupled to the comparator, and configured to generate a first enable signal in response to at least a control signal, and to turn on or turn off the comparator by the first enable signal.

Abstract: An acoustic-wave ladder filter has a first port, a second port and a ground terminal, and includes a series resonator and a shunt circuit. The series resonator is coupled to and disposed between the first and the second ports in series. The shunt circuit is coupled to and disposed between the series resonator and the grounding terminal, and includes a shunt resonator and a functional circuit. The functional circuit is connected in series with the shunt resonator. The functional circuit includes a resistor having a resistance value. The resistance value is greater than 5 Ohms and is smaller than 50 ohms. The functional circuit may further have an inductance.

Abstract: An integrated circuit includes a ramp signal generator circuit, a comparator, a counter and a control circuit. The ramp signal generator circuit is configured to generate a ramp reference signal. The comparator configured to compare a pixel output signal and the ramp reference signal thereby generating a comparator output signal. The counter is coupled to the comparator, and configured to be enabled or disabled in response to the comparator output signal. The control circuit coupled to the comparator, and configured to enable or disable the comparator by a first enable signal, the first enable signal generated in response to at least the comparator output signal.

Abstract: A noise monitoring apparatus includes a row selection circuit, a direct current (DC) cancellation circuit and an amplifier circuit. The row selection circuit selects a row of a DUT array to be a selected row during a readout period, wherein the selected row comprises a plurality of selected DUTs. The DC cancellation circuit is coupled to unselected DUTs of the DUT array during the readout period, generates a DC current signal based on bias current signals from a group of unselected DUTs and subtract the DC current signal from a first noise signal of the selected DUT to generate a second noise signal. The amplifier circuit is coupled to the plurality of selected DUTs of the selected row during the readout period, and amplifies the second noise signal from each of the selected DUTs to generate an output signal.

Abstract: Systems and methods for image stabilization of video imagery generated by applications are disclosed. In some embodiments, an Information Handling System (IHS) may include executable instructions to receive a video stream from an application executed on the IHS, identify a level of jitter in the video stream, and process the video stream by re-positioning imagery in the video stream to compensate for the jitter. The instructions may then display the processed video stream on a display. The display displays the processed video stream in place of the video stream generated by the application.

Abstract: A semiconductor device includes a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, a first mesa isolation on the HEMT region, a HEMT on the first mesa isolation, a second mesa isolation on the capacitor region, and a capacitor on the second mesa isolation. The semiconductor device further includes buffer layer between the substrate, the first mesa isolation, and the second mesa isolation, in which bottom surfaces of the first mesa isolation and the second mesa isolation are coplanar.