Abstract: An integrated circuit includes a comparator, a counter and a control circuit. The comparator is configured to generate a comparator output signal in response to a pixel output signal and a reference signal. The counter is coupled to the comparator, and configured to be enabled or disabled in response to the comparator output signal. The control circuit is coupled to the comparator, and configured to enable or disable the comparator by a first enable signal. The first enable signal is generated in response to at least the comparator output signal.

Abstract: A semiconductor device includes a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, a first mesa isolation on the HEMT region, a HEMT on the first mesa isolation, a second mesa isolation on the capacitor region, and a capacitor on the second mesa isolation. The semiconductor device further includes buffer layer between the substrate, the first mesa isolation, and the second mesa isolation, in which bottom surfaces of the first mesa isolation and the second mesa isolation are coplanar.

Abstract: Systems and methods for image stabilization of video imagery generated by applications are disclosed. In some embodiments, an Information Handling System (IHS) may include executable instructions to receive a video stream from an application executed on the IHS, identify a level of jitter in the video stream, and process the video stream by re-positioning imagery in the video stream to compensate for the jitter. The instructions may then display the processed video stream on a display. The display displays the processed video stream in place of the video stream generated by the application.

Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.

Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.

Abstract: A semiconductor device includes a source/drain diffusion area, a first doped region and a gate. The source/drain diffusion area, defined between a first isolation structure and a second isolation structure, includes a source region, a drain region and a device channel. The first doped region, disposed along a first junction between the device channel and the first isolation structure, is separated from at least one of the source region and the drain region. The first doped region has a dopant concentration higher than that of the device channel. The gate is disposed over the source/drain diffusion area. The first doped region is located within a projected area of the gate onto the source/drain diffusion area, the first isolation structure and the second isolation structure. A length of the first doped region is shorter than a length of the gate in a direction from the source region to the drain region.

Abstract: The present invention provides a light emitting panel, which includes: a substrate, at least one light emitting element disposed on the substrate, and a reflective structure layer. The reflective structure layer includes a plurality of first microstructure units disposed on the substrate and distributed around the at least one light emitting element, and a plurality of second microstructure units disposed on and overlapping the first microstructure units. A spacing between adjacent first microstructure units among the first microstructure units is less than a spacing between adjacent second microstructure units among the second microstructure units.

Abstract: A semiconductor device, a back-side deep trench isolation (BDTI) structure of a semiconductor device, and method of manufacturing a semiconductor structure are provided. The semiconductor device, comprising: a pixel region disposed within a substrate and comprising an image sensing element configured to convert electromagnetic radiation into an electrical signal; and one or more BDTI structures extending from a first-side of the substrate to positions within the substrate; wherein the one or more of BDTI structures comprise one or more ferroelectric materials.

Abstract: A circuit substrate includes a substrate, an active device, a first signal line, a second signal line, a shielding electrode, a data line, a pixel electrode, and a common electrode. The first signal line is electrically connected to the active device, and includes a main portion and a connection portion connected to the main portion. The main portion extends along a first direction. The second signal line extends along a second direction. The second signal line is electrically connected to the connection portion. The shielding electrode overlaps the connection portion in a normal direction of the substrate. The shielding electrode and the second signal line belong to a same conductive layer. The data line is electrically connected to the active device. The common electrode is electrically connected to the shielding electrode.

Abstract: A semiconductor structure includes a semiconductor substrate, an image sensor, and an isolation structure. The isolation structure is adjacent to the image sensor and disposed in the semiconductor substrate. The isolation structure includes a first oxide layer, a second oxide layer over the first oxide layer, and a charge-trapping layer disposed between the first oxide layer and the second oxide layer. The charge-trapping layer includes a material different from those of the first oxide layer and the second oxide layer.

Abstract: The present disclosure provides an optical structure and a method for fabricating an optical structure, the method includes forming a light detection region in a substrate, forming an isolation structure at surrounding the light detection region, and forming a primary grid over the isolation structure, including forming a metal layer over the isolation structure, forming a first dielectric layer over the metal layer, and partially removing the metal layer and the first dielectric layer with a first mask by patterning, and forming a secondary grid at least partially surrounded by the primary grid laterally.

Abstract: A signal filter includes a notch filter and a wideband filter. The notch filter is configured to perform a band-rejection filtering operation according to a band-rejection filtering property. The wideband filter is coupled to the notch filter, and is configured to perform a wideband filtering operation according to a wideband filtering property. The band-rejection filtering property includes a first cutoff frequency, a frequency bandwidth, a relatively high quality factor and a relatively low coupling coefficient. The wideband filtering property includes a second cutoff frequency, a relatively low quality factor and a relatively high coupling coefficient. The first and the second cutoff frequencies have a frequency difference therebetween. A ratio of the frequency difference to the frequency bandwidth is within a preset ratio range being from 2.5% to 20%.

Abstract: A capacitor unit and a manufacturing process thereof are provided. The manufacturing process includes: providing a carrier; forming a metallic layer on the carrier, defining a plurality of metallic blocks in the metallic layer, and forming a middle stacking structure on each of the metallic blocks, wherein the middle stacking structure includes a first capacitance conductive layer, a second capacitance conductive layer, and a capacitance insulation layer located between the first and second capacitance conductive layers, wherein the first capacitance conductive layer is electrically connected to the corresponding one of the metallic blocks; and removing the carrier to expose the metallic blocks so as to form a plurality of independent capacitor units, so as to fabricate double sided capacitor units with high capacitance.

Abstract: A capacitor integrated structure, a capacitor unit and a manufacturing process thereof are provided. The manufacturing process of capacitor units includes the steps of: forming a plurality of capacitor stacking structures on a substrate having an insulation layer thereon; performing a first cut on insulation dividers provided between the adjacent capacitor stacking structures to form a plurality of recesses that expose first conductive portion and second conductive portion of each of the capacitor stacking structures; filling a metallic material in the recesses to form a plurality of metallic dividers that are electrically connected to the first conductive portion and the second conductive portion of each of the capacitor stacking structures; performing a second cut on the metallic dividers to form a plurality of independent capacitor units; and forming metallic walls on two opposite sides of each of the capacitor units, so as to provide a capacitor unit having two end electrodes.

Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.

Abstract: The present disclosure provides an optical structure, including a substrate, a light detection region in the substrate, an isolation structure in the substrate, surrounding the light detection region, a color filter layer over the substrate, and a dielectric grid structure in the color filter layer, the dielectric grid structure overlapping with the light detection region.

Abstract: An acoustic-wave ladder filter has a first port, a second port and a ground terminal, and includes a series resonator and a shunt circuit. The series resonator is coupled to and disposed between the first and the second ports in series. The shunt circuit is coupled to and disposed between the series resonator and the grounding terminal, and includes a shunt resonator and a functional circuit. The functional circuit is connected in series with the shunt resonator. The functional circuit includes a resistor having a resistance value. The resistance value is greater than 5 Ohms and is smaller than 50 ohms. The functional circuit may further have an inductance.

Abstract: An on-chip balun transformer including a primary winding and a secondary winding is provided. The primary winding includes at least one parallel coil and a plurality of first serial semi-turn coils connected to the at least one parallel coil. The secondary winding, magnetically coupled to the primary winding, includes a plurality of second serial semi-turn coils connected to each other. At least one of the second serial semi-turn coils is located within the at least one parallel coil. The primary winding and the secondary winding are coplanar.

Abstract: A mark pattern includes unit cells immediately adjacent to each other and arranged in a form of dot matrix to form a register mark or an identification code, wherein each unit cell has configuration identical to functional devices of pMOS and nMOS, and each unit cell includes a first active region, a second active region isolated from the first active region, and first gate structures extending along a first direction and are arranged along a second direction perpendicular to the first direction, and the first gate structures straddling the first active region and the second active region, contact structures disposed between the first gate structures on the first active region and the second active region, and via structures disposed on the contact structures and two opposite ends of the first gate structures.

Abstract: A pixel array substrate, including multiple pixel structures, multiple data lines, multiple scan line groups, multiple transfer line groups, multiple connection terminal groups, and multiple bridge line groups, is provided. The multiple data lines are electrically connected to the multiple pixel structures and arranged in a first direction. Each scan line group includes multiple scan lines arranged in a second direction. The multiple scan lines of the multiple scan line groups are electrically connected to the multiple pixel structures. Each transfer line group includes multiple transfer lines arranged in the first direction. The multiple transfer lines of each transfer line group are electrically connected to the multiple scan lines of a corresponding scan line group. The bridge line groups are structurally separated. Each bridge line group is electrically connected to a corresponding transfer line group and a corresponding connection terminal group.