Abstract: Polyarylene ether sulfones which have a reduced viscosity of 0.1 to 2.0 dl/g, measured at 25.degree. C. in a 1% solution in N-methylpyrrolidone (NMP), and which contain, based on the total number of structural units present in the polyarylene ether sulfone resin, 99-1 mol % of a recurring structural unit of formula I ##STR1## and 1-99 mol % of a recurring structural unit of formula II--O--Ar.sub.2 --O--Ar.sub.1 -- (II)wherein the aromatic rings in the structural unit of formula I are unsubstituted or substituted by one or more C.sub.1 -C.sub.4 alkyl groups, C.sub.1 -C.sub.4 alkoxy groups or halogen atoms, Ar.sub.1 is a radical of formula IIIa-IIIc ##STR2## wherein a is 0 or 1, ##STR3## which radical is unsubstituted or substituted by one or more C.sub.1 -C.sub.4 alkyl groups, C.sub.1 -C.sub.4 alkoxy groups or halogen atoms, and Ar.sub.2 is a radical of formula IVa-IVe ##STR4## wherein b is 0 or 1 ##STR5## wherein c is 0 or 1 ##STR6## wherein Z is --CO--, --SO.sub.

Abstract: A circuit gives each of the input signals at its inputs to a common circuit previously charged to a supply voltage through transfer transistors. When the logical condition is satisfied the common circuit remains charged; otherwise the charge changes. This is detected by a discriminator circuit and the result is indicated at the circuit output. The circuit may be of AND-, OR-, NAND- and NOR design.

Abstract: An endpiece for a safety ski binding attached to a ski, the endpiece comprising an elongated housing for disposition on the ski in the longitudinal direction of the ski; a lever pivotably mounted to the housing, the lever including a first end having a bolt opening and a second end; a sole holder for exerting a downward force on the sole of a ski boot, and having a portion disposed beneath the lever, the sole holder also having an elongated bore extending substantially perpendicular to the longitudinal axis of the ski; a bolt extending through the bolt opening and the bore, the sole holder vertically slidable on the bolt; a first spring disposed between the housing and the sole holder for urging the sole holder toward the ski; and a second spring for exerting a force on the second end of the lever for resisting rotational movement of the first and of the lever away from the ski.

Abstract: A circuit configuration and method for testing storage cells of an integrated semiconductor memory precharges a pair of external bit lines to mutually complementary logic levels. All of the storage cells of a word line are always read-out in parallel. In a "no fault" situation the pair of external bit lines retains its precharge level, whereas in the case of a fault, the level of the external bit line which is precharged to logical 1 falls. This is recognized by a discriminator circuit and analyzed.

Abstract: A redundancy decoder of an integrated semiconductor memory having a plurality of decoder stages containing a switching transistor and a separable connection having respective conditions in which the separable connection is severed and intact, as well as at least one charging transistor, comprising, in each of the decoder stages, an addressing circuit connected to and between the switching transistor and the separable connection of the respective decoder stages, the addressing circuit being electrically simulatable when the respective separable connection is in the intact condition thereof.

Abstract: A multi-stage integrated decoder device has a special function which facilitates the simultaneous activation of a plurality and as many as all of its outputs. When it is used as a bit line decoder it is thus possible to activate a plurality and as many as all of the bit lines (including any redundant bit lines) of a block of storage cells of a semiconductor memory.

Abstract: In a circuit configuration and a method for testing storage cells, all of the bit lines lead to one pair of fault lines which is first precharged with mutually-complementary logic levels. All of the storage cells of a word line are always read-out in parallel relative to one another. In the event of "no fault" the pair of fault lines retains its logic states, whereas in the case of a fault one of the fault lines changes its logic state through switching transistors. This is recognized and analyzed by a comparator circuit in the form of an XOR-circuit or an XNOR-circuit.

Abstract: A method and circuit configuration for the parallel input of data items in the form of a test pattern into a block of a semiconductor memory having a plurality of storage cells. For test purposes, data items are simultaneously input in parallel into the storage cells.

Abstract: A multi-stage, integrated decoder device includes a special function which facilitates the simultaneous activation of a plurality or as many as all of its outputs while gating out a pre-selectible output. When used as bit line decoder, it is thus possible to activate a plurality or up all of the bit lines (including any redundancy bit lines) of a block of storage cells of a semiconductor memory, excluding a bit line assumed to contain at least one defective storage cell.

Abstract: An integrated semiconductor memory includes n identical memory cell fields each having a data width equal to m, n.multidot.m data lines for writing-in and reading-out memory data into and out of the memory cell fields, m first data separators for applying the memory data as a function of addressing data when written-in, m second data separators for selecting one of the n data lines in response to the addressing data. It further has evaluation circuits connected to n of the n.multidot.m data lines parallel to the respective second data separators. It also has third data separators connected between each of the m data input terminals and the n of n.multidot.

Abstract: Integrated semiconductor memory includes n identical memory cell fields, each having a data width equal to m, n .

Abstract: Monolithically integrated semiconductor circuit with transistors, the semiconductor circuit proper having elements thereof formed on the front side of a semiconductor chip, the latter also having at the surface thereof two supply terminals actable upon by a respective supply potential and connected, on the one hand, to the elements of the semiconductor circuit proper and, on the other hand, to an additional circuit part for generating a substrate bias applied to a substrate region occupying the rear side of the semiconductor chip and, respectively, to at least one semiconductor zone belonging to the semiconductor circuit proper and to a gate electrode on the front side of the semiconductor chip which controls the semiconductor zone and is insulated therefrom, including a series connection of the substrate bias generator and the semiconductor circuit proper dividing a voltage present at the two supply terminals of the semiconductor chip in a manner that a reference potential required for the semiconductor circ

Abstract: Monolithically integrated semiconductor memory with a matrix of identical storage cells arranged rows and columns in the form of a coordinated MOS field-effect transistors and storage capacitors in the form of an MOS capacitor and wherein, also, a comparator and a comparison cell is formed of one of the storage cells are associated with each matrix column, including a method for bridging over a point of interruption in a course of a bit line extending from one to another of at least two adjacent storage cells of at least one column. The bridging method may be an MOS field-effect transistor having a current-carrying path over which the point of interruption is bridged.

Abstract: A semiconductor circuit assembly having capacitively controlled field effect transistors, includes a semiconductor chip containing a digital circuit part for supplying timing pulses for controlling operation of the digital circuit part, and terminal having at least one conductive connection to the digital circuit part and the timing pulse generator for supplying potentials thereto from a direct current source. An oscillator is provided and a substrate-bias generator connected to the oscillator and the timing pulse generator. The substrate-bias generator is controlled by the oscillator for producing a bias voltage able to reach a given full value and for activating the timing pulse generator only after the substrate bias voltage has reached its full value.

Abstract: Monolithically integrated semiconductor memory, including a matrix of identical memory cells disposed in a set of row members and a set of column members, each of the memory cells including a single MOS-field effect transistor and a storage capacitor, a comparator, and a comparison cell, the comparison cell being in the form of a memory cell including a single MOS-field effect transistor and a storage capacitor, the comparator and the comparison cell being assigned to each of the members of one of the sets, each of the comparators within the matrix of single-transistor memory cells including a flip-flop memory cell constructed in complimentary MOS-technology.

Abstract: MOS integrated circuit arrangement for suppressing quiescent currents flowing in word line drivers of semiconductor memories, including respective controlled switches addressed by a storage activation signal, the controlled switches being connected between the output circuit of the word line drivers and reference potential.

Abstract: An MOS integrated semiconductor memory is disclosed with memory locations arranged in lines and columns. The memory locations in each case contain two one-transistor memory cells. For each memory location, two MOS transistors of the two one-transistor memory cells are controlled in common by means of a word line which runs in a line direction. The two MOS transistors are each coupled on a respective bit line which runs on one side of the memory locations in a column direction. Electrodes of the MOS memory capacitors and the gates of the MOS transistors of the one-transistor memory cells are formed by a first polysilicon layer and a second polysilicon layer, respectively.

Abstract: A clock-controlled dc converter is provided in integrated semiconductor MOS technology and serves the supply voltage of integrated MOS circuits, particularly dynamic memories. The converter comprises a clock pulse generator having two outputs, supplying sequences of clock pulses which are inverted with respect to one another, which pulses are connected to the two clock pulse inputs of a first pulse level shifter. The first pulse level shifter comprises a bistable flip-flop lying at a supply potential, and which is switched as a level shifter. The two outputs of the first level shifter are connected, on the one hand, to the output of a voltage converter by way of the source-drain circuit of a respective field effect transistor. On the other hand, the two outputs are connected to the supply input of a respective pulse voltage doubler, which are in turn directly charged by a respective output of the clock pulse generator.

Abstract: A monolithically integrated MOS-circuit with a substrate bias voltage generator is disclosed. A generator, a control loop, a threshold voltage detector, and a pump circuit are provided. An acceleration of the regulation of the substrate bias voltage is achieved wherein the output signal of an oscillator is connected to the Reset or Set input of a RS flip-flop. The two outputs of the flip-flop are applied in common to the substrate of the MOS-circuit via a respective pump circuit. A control loop with the threshold voltage detector serving for the regulation of the substrate bias voltage controls the flip onset via an additional input of the flip-flop and, thus, the substrate bias voltage.

Abstract: A digital CCD arrangement is provided in which an output signal is emitted which is regenerated with respect to its voltage range, and is substantially insensitive to adverse influences. In this arrangement, the last shift electrode preceding the output end zone is coupled with respect to potential to a circuit point of a transistor stage, which point in the event of a quantity of charge carriers representing logic level "1," the output end zone experiences a change in potential which corresponds to the change in potential beneath the other shift electrodes. Between the last preceding shift electrode and the output end zone, there is arranged a further electrode which is insulated from the semiconductor layer and is connected to a second reference potential which corresponds to an intermediate value which is swept over by the potential across the circuit point.