Abstract: A one-transistor storage element system and a method for producing the same is disclosed wherein each storage element has a sselector field effect transistor and a storage capacitor. A doped semiconductor layer is provided having an oppositely doped bit line provided at a surface thereof, an oppositely doped source zone connecting to the bit line by an oppositely doped connecting zone, and an oppositely doped drain zone also provided at a surface of the semiconductor layer. An insulating layer is provided over the surface of the semiconductor layer and an electrically conductive coating is provided thereon. A first separate part of the conductive coating forms a word line which is positioned over a gap between the source and drain zones. Portions of the word line form a gate beneath which a channel of the transistor is formed.

Abstract: A semiconductor storage element is disclosed having a storage capacitor whose storage electrode is arranged above a doped semiconductor layer. The storage electrode is formed of a portion of a strip-like reference potential line which is separated from the semiconductor layer by a thin insulating layer. A transfer gate is also provided adjacent to the storage electrode which is formed from a portion of a strip-like word line likewise separated from the semiconductor layer by a thinner insulating layer. An oppositely doped zone is arranged at a surface of the semiconductor layer and serves as a bit line. The word line and the reference potential line run parallel to one another and are arranged directly adjacent to one another. When a potential is connected to the transfer gate, the bit line doped zone may be selectively conductively connected to the storage zone. The reference potential line for one group of the storage elements can be also used as a word line for another group of the storage elements.

Abstract: In the production of V-MOS single transistor memory cells a simplification of the previous technology is disclosed wherein a process is utilized without epitaxial processes and with a minimum of doping processes. First the source and the drain zone of a field effect transistor forming a memory cell are produced and only then is a V-shaped recess formed at the site of these zones. In one embodiment, one re-doped zone is constructed as a flat zone and is produced on both sides adjacent to a second re-doped zone extending deeper into the silicon crystal. The V-shaped recess is then etched in such a way that the two zones are completely separated by the V-shaped recess. The silicon surface in the V-shaped recess is provided with a thin SiO.sub.2 layer and with a gate electrode covering it. Advantageously the gate electrodes of neighboring V-MOS cells are united into a line. This occurs with one of the two zones of the transistor, whereas the other zone remains separate.

Abstract: An arrangement, particularly an analog-digital converter having a resistance line or chain, and a plurality of voltage comparators, each preferably comprising an insulator-layer, field-transistor and a load element in the form of a resistance, capacitor or diode, in which the control electrode terminal of each transistor forms a first comparator input, which is connected to a respective point on the resistance and with each cooperable load element being connected to one of the two remaining transistor terminals, one of which also simultaneously forms the output of such voltage comparator, and with the second comparator input for such voltage comparator being formed by the other transistor terminal.

Abstract: A semiconductor memory has at least one V-MOS transistor which includes a trench and a storage capacitor. A semiconductor substrate is doped with concentration centers of a first conductivity type and has a buried layer which is doped with concentration centers of a second conductivity type opposite to the first conductivity type. At least two additional layers are divided by the trench and have alternately differing conductivity types, the two additional layers and the buried layer being produced by diffusion and/or implantation.

Abstract: A method and apparatus is disclosed for a fast switching digital differential amplifier system useful in regenerating information signals in charge coupled devices. The amplifier system has a first capacitance at an input point which is charged and discharged in accordance with a binary "0" or binary "1" at the input. A second capacitance and an output capacitance is provided with a predetermined charge thereon. In the event of a binary "1", the predetermined charge on the second and output capacitance is retained while the first capacitance is discharged. In the event of a binary "0", the second and output capacitances are discharged via a current sink. A flip-flop is connected to the output capacitance for accelerating the discharge of the same. Switching transistors are additionally provided for activating the flip-flop to achieve the desired fast-switching.

Abstract: Regenerating amplifier for use with two charge coupled devices comprising field effect transistors to pre-charge the output diffusion capacitance of an output charge coupled device and the input diffusion capacitance of an input charge coupled device. The output diffusion capacitance is discharged by the arrival of output charge, in turn holding off an input gate such that the charge on the input diffusion capacitance is not shifted into the input charge coupled device. Various embodiments having control potentials and a field effect transistor to fully discharge the input diffusion capacitance of an input charge coupled device being usable with a plurality of input charge coupled devices having corresponding output charge coupled devices wherein individual charging transistors are available to charge each output diffusion zone capacitance with a common transistor being used to charge all input diffusion capacitances.

Abstract: An arrangement, particularly an analog-digital/digital-analog converter having a resistance line or chain, and a plurality of voltage comparators, each preferably comprising an insulator-layer, field-transistor and a load element in the form of a resistance, capacitor or diode, in which the control electrode terminal of each transistor forms a first comparator input, which is connected to a respective point on the resistance and with each cooperable load element being connected to one of the two remaining transistor terminals, one of which also simultaneously forms the output of such voltage comparator, and with the second comparator input for such voltage comparator being formed by the other transistor terminal.

Abstract: Regenerating amplifier for use with charge coupled devices comprising a pair of diode-coupled transistors connected to an output terminal of one charge coupled device, two capacitances, and means for precharging said two capacitances. One of the capacitances is a parasitic capacitance, the other of which is the input capacitance of the second charge coupled device. The charge is transferred from the output terminal of the first charge coupled device by discharging one precharged capacitor and thus discharging or not discharging the second capacitance at the input to the second charge coupled device, depending upon the binary state of the data being transferred.

Abstract: Digital differential amplifier with pre-chargeable parasitic capacitances to switch on or hold blocked output transistors discharging or not discharging an output capacitance via a constant current sink for a combination of two charge coupled devices. The digital differential amplifier detects the presence or absence of charge on the output of a first charge coupled device and inputs a corresponding charge to a second charge coupled device. The combination of the two charge coupled devices with two digital differential amplifiers and two control transistors is such that stored charges may be recirculated between the two charge coupled devices or previously stored data may be serially read from the output of one charge coupled device and new data may be serially written into the input of the other charge coupled device. A method of recirculating previously stored data or writing new data into the second charge coupled device using precharged parasitic and diffusion zone capacitances is also described.

Abstract: A line as disclosed for transporting charges from one point to another. The substrate of semiconductive material has an electrical insulating layer arranged thereon. Upon this layer, a resistive layer is applied having electrodes at end points thereof for producing a drift field. Diffusion areas are arranged at the end points which are oppositely doped with respect to the semiconductor material situated under the conductive layer. Storage elements in a storage field are connected to the line and write/read circuits are positioned at ends of the line. Taps may be connected at intermediate points along the line to permit application of differing voltages to enhance charge shifting along the line.

Abstract: Regenerator circuit for CCD elements in which charge representing information is transferred from a first CCD element to a second CCD element. The circuit includes a first MOS capacitance and a second capacitance connected in series with the first capacitance, the point at which the two capacitances are connected with one another being connected to the input of said second CCD. The output of the first CCD includes an output stage having an output diffusion zone. A transistor is connected between a terminal to which a potential .phi..sub.v can be connected and the point between said first and second capacitances. This transistor has a gate electrode which is connected by a line to the output diffusion zone of the first CCD.

Abstract: A three-transistor storage element is disclosed which includes a first load element, a first field effect transistor and a second load element connected in series between first and second terminal lines of a voltage supply. Node points are located at opposite ends of the first transistor in the series path between the first load element and the first transistor and between the second load element and the first transistor. A second field effect transistor is connected between the first terminal line and the second node point. The gate of said second transistor is connected to the first node point. The gate of the first transistor is connected to a reference voltage. An address field effect transistor is connected between a bit line and the second node point and the gate of said address transistor is connected to a word line. A modified form of this storage element is one in which the load elements are in the form of fourth and fifth field effect transistors.

Abstract: A static storage element circuit has two pairs of complementary-channel-field effect transistors. A word line and a bit line connect with at least one of the field effect transistors. Connection lines between the field effect transistors create parasitic capacitors for storing charges which control the logic state of the circuit.