Abstract: A circuit for controlling driver strengths of a data and a data strobe in a semiconductor device comprising: a control signal generating unit which generates a first control signal in response to a first address code, generates a second control signal in response to a second address code, and generates a third control signal in response to a third address code; a data driver strength control unit which is selected in response to the first control signal, controls a driver strength of an input data in response to the second control signal, and finely adjusts the driver strength of the input data in response to the third control signal; and a data strobe driver strength control unit which is selected in response to the first control signal, controls a driver strength of an input data strobe in response to the second control signal, and finely adjusts the driver strength of the input data strobe in response to the third control signal.

Abstract: A hole driver for driving a hole in a semiconductor memory device, including a first bank controller for generating a control signal for controlling a X-hole of a first bank in response to a row active signal and a precharge signal for the first bank, a second bank controller for generating a control signal for controlling a X-hole of a second bank in response to a row active signal and a precharge signal for the second bank, a block address enable means for generating a common block address enable signal in response to output signals of the first and the second bank control means and a common block address predecoder for predecoding block address signal for each bank in response to the common block address enable signal.

Abstract: An apparatus for a pipe latch control circuit controlled by a pipe output control signal in a synchronous memory device. The apparatus includes a plurality of counting stages for counting in sequence in response to a data output buffer drive signal and a counting signal driver for generating the pipe output control signal by driving each counting signal, which is outputted from the plurality of counting stages and controlled by the data output buffer drive signal.

Abstract: A synchronous memory device is capable of reducing the number of address pins by changing address input. The synchronous memory device includes at least one common pin receiving a first signal and a second signal, latch circuits coupled to the common pin, wherein the latch circuit latches the first and second signals and one of the latch circuits selectively outputs the first or second signal in response to first or second internal clock pulses, and a clock pulse generator for receiving an external clock signal and for producing the first and second internal clock pulses from the external clock signal.

Abstract: A synchronous memory device which comprises global I/O lines for data input and output from and to a memory core and a pipeline latch circuit for latching data from the global I/O lines. The synchronous memory device includes a circuit that precharges the global I/O lines when a read command signal interrupts a write operation signal, and disables the pipeline latch circuit in order to prevent write data on the global I/O lines from being latched in the pipeline latch circuit. Accordingly, the write data is prevented from being transferred to the pipeline latch circuit at an early stage of the read operation.

Abstract: A hole driver for driving a hole in a semiconductor memory device, including a first bank controller for generating a control signal for controlling a X-hole of a first bank in response to a row active signal and a precharge signal for the first bank, a second bank controller for generating a control signal for controlling a X-hole of a second bank in response to a row active signal and a precharge signal for the second bank, a block address enable means for generating a common block address enable signal in response to output signals of the first and the second bank control means and a common block address predecoder for predecoding block address signal for each bank in response to the common block address enable signal.

Abstract: A synchronous memory device is capable of reducing the number of address pins by changing address input. The synchronous memory device includes at least one common pin receiving a first signal and a second signal, latch circuits coupled to the common pin, wherein the latch circuit latches the first and second signals and one of the latch circuits selectively outputs the first or second signal in response to first or second internal clock pulses, and a clock pulse generator for receiving an external clock signal and for producing the first and second internal clock pulses from the external clock signal.

Abstract: An apparatus for a pipe latch control circuit controlled by a pipe output control signal in a synchronous memory device, comprising: a plurality of counting stages for counting in sequence in response to a data output buffer drive signal and a counting signal driver for generating the pipe output control signal by driving each counting signal, which is outputted from the plurality of counting stages and controlled by the data output buffer drive signal.

Abstract: A global input/output precharge apparatus includes a latch for cross-coupling and latching a global input/output line and a complementary global input/output line; a global input/output line delay for delaying the global input/output line and the complementary global input/output line by a predetermined time delay; a global input/output line precharge logic for pre-charging the global input/output line feed-backed from the global input/output line delay; a first precharge logic for applying a power voltage to the global input/output line when a first logic state is feed-backed on the output of the global input/output line precharge logic and applying a ground voltage to the global input/output line when a second logic state is feed-backed on the output of the global input/output line precharge logic; and a second precharge logic for applying the power voltage to the complementary global input/output line when the first logic state is feed-backed on the output of the global input/output line precharge logic an

Abstract: A synchronous memory device which comprises global I/O lines for data input and output from and to a memory core and a pipeline latch circuit for latching data from the global I/O lines. The synchronous memory device includes a circuit that precharges the global I/O lines when a read command signal interrupts a write operation signal, and disables the pipeline latch circuit in order to prevent write data on the global I/O lines from being latched in the pipeline latch circuit. Accordingly, the write data is prevented from being transferred to the pipeline latch circuit at an early stage of the read operation.

Abstract: A global input/output precharge apparatus includes a latch for cross-coupling and latching a global input/output line and a complementary global input/output line; a global input/output line delay for delaying the global input/output line and the complementary global input/output line by a predetermined time delay; a global input/output line precharge logic for pre-charging the global input/output line feed-backed from the global input/output line delay; a first precharge logic for applying a power voltage to the global input/output line when a first logic state is feed-backed on the output of the global input/output line precharge logic and applying a ground voltage to the global input/output line when a second logic state is feed-backed on the output of the global input/output line precharge logic; and a second precharge logic for applying the power voltage to the complementary global input/output line when the first logic state is feed-backed on the output of the global input/output line precharge logic an

Abstract: A memory device having a plurality of pipelatch circuits storing data from memory cells via global input/output lines, a pipelatch input control circuit to selectively couple the pipelatch circuit to the global input/output lines in response to a pipelatch control signal, and a pipe count signal generator to control a data path between the pipelatch circuits and an output driver, wherein the pipelatch input control circuit includes: a first control signal generator receiving a first control signal and global input/output line signals and producing a pass gate control signal; a second control signal generator receiving the first control signal and the pass gate control signal and producing a plurality of second control signals; a third control signal generator receiving the pass gate control signal and producing a third control signal by combining the pass gate control signal and a delay signal of the pass gate control signal; and a fourth control signal generator receiving the first control signal, the plural

Abstract: A synchronous memory device having an apparatus for generating a data strobe signal, the apparatus for generating a data strobe signal includes: a preamble control unit for controlling a preamble state of a data strobe signal in response to a data strobe preamble control signal; at least one pair of pull-up/pull-down signal generating unit coupled to the preamble control unit, for receiving pipe counter signals at a first input terminal to generate pull-up and pull-down signals; a common pull-up signal buffering unit for buffering the pull-up signal to generate a buffered pull-up signal, wherein the buffered pull-up signal is commonly inputted to a second input terminal of the pull-up/pull-down signal generating unit; a common pull-down signal buffering unit for buffering the pull-up signal to generate a buffered pull-down signal, wherein the buffered pull-down signal is commonly inputted to a third input terminal of the pull-up/pull-down signal generating unit; and a data strobe signal driving unit for outpu

Abstract: Disclosed is a data strobe signal generator of the SDRAM device. The data strobe signal generator according to the present invention does not have to use a current output state signal generator, by using a pipe counter signal which has been issued at the previous read operation, thereby proving various advantages, such as simple circuit design, simple operation and small chip size. A data strobe signal generator in a SDRAM memory device, includes: a preamble controller for controlling a preamble state of a data strobe signal in response to a control signal; a plurality of pull-up/pull-down signal drivers for producing pull-up and pull-down signals through a toggling operation in response to previous pull-down and pull-up signals; and a data strobe signal driver for outputting the data strobe signal in response to the pull-up and pull-down signals.

Abstract: A multilevel sensing circuit and sensing method therefor. The multilevel sensing circuit has first and second sense amplifiers connected to each bit line to which left and right memory cells of a DRAM are connected, a feedback element connected to each bit line, and an isolating transistor including an NMOS transistor connected between the comparator and a sensing input node of the second sense amplifier. The isolating transistor is turned on after a second sensing operation is sufficiently carried out and turned off before a restore operation is carried out.