Patents by Inventor Kwan-Yong Lim

Kwan-Yong Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9812452
    Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 7, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kwan-Yong Lim, James Walter Blatchford, Shashank S. Ekbote, Younsung Choi
  • Patent number: 9799751
    Abstract: One illustrative method disclosed herein includes forming a multi-layered sidewall spacer (MLSS) around a vertically oriented channel semiconductor structure, wherein the MLSS comprises a non-sacrificial innermost first spacer (a high-k insulating material), a sacrificial outermost spacer and at least one non-sacrificial second spacer (a metal-containing material) positioned between the innermost spacer and the outermost spacer, removing at least a portion of the sacrificial outermost spacer from the MLSS while leaving the at least one non-sacrificial second spacer and the non-sacrificial innermost first spacer in position and forming a final conductive gate electrode in place of the removed sacrificial outermost spacer.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: October 24, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: John H. Zhang, Steven J. Bentley, Kwan-Yong Lim
  • Publication number: 20170301776
    Abstract: One illustrative method disclosed herein includes forming a multi-layered sidewall spacer (MLSS) around a vertically oriented channel semiconductor structure, wherein the MLSS comprises a non-sacrificial innermost first spacer (a high-k insulating material), a sacrificial outermost spacer and at least one non-sacrificial second spacer (a metal-containing material) positioned between the innermost spacer and the outermost spacer, removing at least a portion of the sacrificial outermost spacer from the MLSS while leaving the at least one non-sacrificial second spacer and the non-sacrificial innermost first spacer in position and forming a final conductive gate electrode in place of the removed sacrificial outermost spacer.
    Type: Application
    Filed: April 19, 2016
    Publication date: October 19, 2017
    Inventors: John H. Zhang, Steven J. Bentley, Kwan-Yong Lim
  • Publication number: 20170278844
    Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level.
    Type: Application
    Filed: March 28, 2016
    Publication date: September 28, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Min Gyu Sung, Chanro Park, Hoon Kim, Ruilong Xie, Kwan-Yong Lim
  • Patent number: 9773708
    Abstract: Devices and methods of fabricating vertical field effect transistors on semiconductor devices are provided. One intermediate semiconductor includes: a substrate, a bottom spacer layer above the substrate, a plurality of fins, wherein at least one fin is an n-fin and at least one fin is a p-fin; a high-k layer and a work function metal over the bottom spacer layer and around the plurality of fins; a top spacer above the high-k layer and the work function metal and surrounding a top area of the fins; a top source/drain structure over each fin; a dielectric capping layer over the top source/drain structure; a fill metal surrounding the work function metal; and a liner.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: September 26, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: John Zhang, Steven Bentley, Kwan-Yong Lim
  • Publication number: 20170271163
    Abstract: Methodologies and a device for SRAM patterning are provided. Embodiments include forming a spacer layer over a fin channel, the fin channel being formed in four different device regions; forming a bottom mandrel over the spacer layer; forming a top mandrel directly over the bottom mandrel, wherein the top and bottom mandrels including different materials; forming a buffer oxide layer over the top mandrel; forming an anti-reflective coating (ARC) over the first OPL; forming a photoresist (PR) over the ARC and patterning the PR; and etching the first OPL, ARC, buffer oxide, and top mandrel with the pattern of the PR, wherein a pitch of the PR as patterned is different in each of the four device regions.
    Type: Application
    Filed: March 17, 2016
    Publication date: September 21, 2017
    Inventors: Min Gyu SUNG, Ruilong XIE, Chanro PARK, Hoon KIM, Kwan-Yong LIM
  • Patent number: 9761662
    Abstract: Methods form structures to include a first pair of complementary transistors (having first and second transistors) and a second pair of complementary transistors (having third and fourth transistors). An active area of the first transistor contacts an active area of the second transistor along a first common edge that is straight, and an active area of the third transistor contacts an active area of the fourth transistor along a second common edge that is straight and parallel to the first common edge. The active area of the second transistor has a third edge, opposite the first common edge, that has a non-linear shape, and the active area of the third transistor has a fourth edge, opposite the second common edge, that has the same non-linear shape. The non-linear shape of the third edge faces and is inverted relative to the non-linear shape of the fourth edge.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: September 12, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Bipul C. Paul, Kwan-Yong Lim
  • Patent number: 9711511
    Abstract: A semiconductor memory structure (e.g., SRAM) includes vertical channels with a circular, square or rectangular cross-sectional shape. Each unit cell can include a single pull-up vertical transistor and either: one pull-down vertical transistor and one pass-gate vertical transistor; or two or more of each of the pull-down and pass-gate vertical transistors. The structure may be realized by providing adjacent layers of undoped semiconductor material, forming vertical channels for vertical transistors, the vertical channels situated on each of the adjacent layers, doping a first half of each of the adjacent layers with a n-type or p-type dopant, doping a second half of each of the adjacent layers with an opposite type dopant to that of the first half, forming wrap-around gates surrounding the vertical channels, and forming top electrodes for the vertical transistors.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: July 18, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kwan-Yong Lim, Ryan Ryoung-Han Kim, Motoi Ichihashi, Youngtag Woo, Deepak Nayak
  • Publication number: 20170200797
    Abstract: At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins.
    Type: Application
    Filed: March 29, 2017
    Publication date: July 13, 2017
    Inventors: Kwan-Yong Lim, Christopher Michael Prindle
  • Publication number: 20170141211
    Abstract: One illustrative integrated circuit product disclosed herein includes, among other things, a plurality of FinFET devices, each of which comprises a gate structure comprising a high-k gate insulation material and at least one layer of metal, a single diffusion break (SDB) isolation structure positioned in a first trench defined in a semiconductor substrate between first and second active regions, the SDB isolation structure comprising the high-k insulating material and the at least one layer of metal, and a double diffusion break (DDB) isolation structure positioned in a second trench defined in a semiconductor substrate between third and fourth active regions, the DDB isolation structure comprising a first insulating material that substantially fills the second trench.
    Type: Application
    Filed: May 31, 2016
    Publication date: May 18, 2017
    Inventors: Ruilong Xie, Kwan-Yong Lim, Min Gyu Sung, Ryan Ryoung-Han Kim
  • Patent number: 9640636
    Abstract: One illustrative method disclosed herein includes, among other things, forming an initial vertically oriented channel semiconductor structure having a first height above a substrate, forming a sacrificial spacer structure adjacent the initial vertically oriented channel semiconductor structure and, with the sacrificial spacer in position, performing at least one process operation to define a self-aligned bottom source/drain region for the device that is self-aligned with respect to the sacrificial spacer structure, forming an isolation region in the trench and forming a bottom source/drain electrode above the isolation region. The method also includes removing the sacrificial spacer structure and forming a bottom spacer material around the vertically oriented channel semiconductor structure above the bottom source/drain electrode.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: May 2, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven J. Bentley, John H. Zhang, Kwan-Yong Lim, Hiroaki Niimi
  • Patent number: 9640533
    Abstract: At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: May 2, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kwan-Yong Lim, Christopher Michael Prindle
  • Publication number: 20170047329
    Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.
    Type: Application
    Filed: October 27, 2016
    Publication date: February 16, 2017
    Inventors: Kwan-Yong LIM, James Walter BLATCHFORD, Shashank S. EKBOTE, Younsung CHOI
  • Patent number: 9543215
    Abstract: A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor structure, the structure including a semiconductor substrate having a n-type device region and a p-type device region, the p-type device region including an upper layer of p-type semiconductor material, a hard mask layer over both regions, and a mask over the structure for patterning at least one fin in each region. The method further includes creating partial fin(s) in each region from the starting semiconductor structure, creating a conformal liner over the structure, creating a punch-through-stop (PTS) in each region, causing each PTS to diffuse across a top portion of the substrate, and creating full fin(s) in each region from the partial fin(s).
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: January 10, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kwan-Yong Lim, Steven John Bentley, Chanro Park
  • Patent number: 9536793
    Abstract: Methods for self-aligned gate-first VFETs using gate-spacer recess and the resulting devices are disclosed.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: January 3, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John H. Zhang, Kwan-Yong Lim, Steven John Bentley, Chanro Park
  • Patent number: 9530863
    Abstract: One illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure, forming a layer of a bottom spacer material around the vertically oriented channel semiconductor structure and forming a sacrificial material layer above the layer of a bottom spacer material. In this example, the method further includes forming a sidewall spacer adjacent the vertically oriented channel semiconductor structure and above an upper surface of the sacrificial material layer, removing the sacrificial material layer so as to define a replacement gate cavity between a bottom surface of the sidewall spacer and the layer of a bottom spacer material, and forming a replacement gate structure in the replacement gate cavity.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: December 27, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: John H. Zhang, Carl Radens, Steven J. Bentley, Brian A. Cohen, Kwan-Yong Lim
  • Patent number: 9530866
    Abstract: Forming a first sidewall spacer adjacent a vertically oriented channel semiconductor structure (“VCS structure’) and adjacent a cap layer, performing at least one planarization process so as to planarize an insulating material and expose an upper surface of the cap layer and an upper surface of the first spacer and removing a portion of the first spacer and an entirety of the cap layer so as to thereby expose an upper surface of the VCS structure and define a spacer/contact cavity above the VCS structure and the first spacer. The method also includes forming a second spacer in the spacer/contact cavity, forming a top source/drain region in the VCS structure and forming a top source/drain contact within the spacer/contact cavity that is conductively coupled to the top source/drain region, wherein the conductive contact physically contacts the second spacer in the spacer/contact cavity.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: December 27, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: John H. Zhang, Carl Radens, Steven J. Bentley, Brian A. Cohen, Kwan-Yong Lim
  • Patent number: 9508601
    Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: November 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kwan-Yong Lim, James Walter Blatchford, Shashank S. Ekbote, Younsung Choi
  • Publication number: 20160307807
    Abstract: A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor structure, the structure including a semiconductor substrate having a n-type device region and a p-type device region, the p-type device region including an upper layer of p-type semiconductor material, a hard mask layer over both regions, and a mask over the structure for patterning at least one fin in each region. The method further includes creating partial fin(s) in each region from the starting semiconductor structure, creating a conformal liner over the structure, creating a punch-through-stop (PTS) in each region, causing each PTS to diffuse across a top portion of the substrate, and creating full fin(s) in each region from the partial fin(s).
    Type: Application
    Filed: April 20, 2015
    Publication date: October 20, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Kwan-Yong LIM, Steven John BENTLEY, Chanro PARK
  • Publication number: 20160268257
    Abstract: At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins.
    Type: Application
    Filed: March 12, 2015
    Publication date: September 15, 2016
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Kwan-Yong Lim, Christopher Michael Prindle