Patents by Inventor Kwan-Yong Lim

Kwan-Yong Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130285144
    Abstract: A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, and a channel region with a protrusion structure formed in the substrate of the first region, a gate insulating layer formed over the substrate, a first polysilicon layer filling the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.
    Type: Application
    Filed: June 25, 2013
    Publication date: October 31, 2013
    Inventors: Kwan-Yong LIM, Heung-Jae Cho, Min-Gyu Sung
  • Publication number: 20130241011
    Abstract: A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer.
    Type: Application
    Filed: May 10, 2013
    Publication date: September 19, 2013
    Applicant: SK hynix Inc.
    Inventors: Kwan-Yong Lim, Hong-Seon Yang, Heung-Jae Cho, Tae-Kyung Kim, Yong-Soo Kim, Min-Gyu Sung
  • Patent number: 8471338
    Abstract: A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, a channel region with a recessed structure formed in the first region of the substrate, a gate insulating layer formed over the substrate, a first polysilicon layer filled into the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: June 25, 2013
    Assignee: Hynix Semiconductor
    Inventors: Kwan-Yong Lim, Heung-Jae Cho, Min-Gyu Sung
  • Patent number: 8441079
    Abstract: A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: May 14, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwan-Yong Lim, Hong-Seon Yang, Heung-Jae Cho, Tae-Kyung Kim, Yong-Soo Kim, Min-Gyu Sung
  • Patent number: 8440560
    Abstract: A method for fabricating a tungsten (W) line includes forming a silicon-containing layer, forming a diffusion barrier layer over the silicon-containing layer, forming a tungsten layer over the diffusion barrier layer, and performing a thermal treatment process on the tungsten layer to increase a grain size of the tungsten layer.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: May 14, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min-Gyu Sung, Heung-Jae Cho, Kwan-Yong Lim
  • Patent number: 8395266
    Abstract: A semiconductor memory device includes a titanium layer and a titanium nitride layer formed on a substrate, a thin layer formed on the titanium nitride layer, and a metal layer formed on the thin layer, wherein the thin layer increases a grain size of the metal layer.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: March 12, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwan-Yong Lim, Min-Gyu Sung, Heung-Jae Cho
  • Patent number: 8330211
    Abstract: A memory device includes a substrate, a plurality of wordlines arranged over the substrate, a plurality of pillars formed over the substrate between the wordlines, a gate electrode surrounding external walls of the pillars to be connected to the wordlines, and an insulation layer for insulating one sidewall of each wordline from the gate electrode.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: December 11, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min-Gyu Sung, Kwan-Yong Lim
  • Patent number: 8330215
    Abstract: A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 11, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwan-Yong Lim, Hong-Seon Yang, Dong-Sun Sheen, Se-Aug Jang, Heung-Jae Cho, Yong-Soo Kim, Min-Gyu Sung, Tae-Yoon Kim
  • Patent number: 8319341
    Abstract: A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-based electrode. An intermediate structure, which includes a titanium layer and a tungsten silicide layer, is formed over the polysilicon-based electrode. A metal electrode is formed over the intermediate structure.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: November 27, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min-Gyu Sung, Hong-Seon Yang, Heung-Jae Cho, Yong-Soo Kim, Kwan-Yong Lim
  • Patent number: 8288819
    Abstract: A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: October 16, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong Soo Kim, Hong Seon Yang, Se Aug Jang, Seung Ho Pyi, Kwon Hong, Heung Jae Cho, Kwan Yong Lim, Min Gyu Sung, Seung Ryong Lee, Tae Yoon Kim
  • Patent number: 8237220
    Abstract: In a high speed vertical channel transistor, a pillar structure is formed over a substrate, a gate electrode surrounds an outer wall of a lower portion of the pillar structure; and a word line extends in a direction to partially contact an outer wall of the gate electrode. The word line shifts toward a side of the pillar structure resulting in increased transistor speed.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: August 7, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min-Gyu Sung, Heung-Jae Cho, Yong-Soo Kim, Kwan-Yong Lim, Se-Aug Jang
  • Patent number: 8227920
    Abstract: A semiconductor device includes a substrate, a pattern including a conductive layer and a hard mask layer stacked over the substrate, a capping layer surrounding sidewalls of the pattern, and a stress buffer layer disposed between the hard mask layer and the capping layer. The stress buffer layer is configured to inhibit transfer of stress between the hard mask layer and the capping layer during a thermal process so as to inhibit leaning of the capping layer.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: July 24, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min-Gyu Sung, Heung-Jae Cho, Kwan-Yong Lim
  • Publication number: 20120135576
    Abstract: Provided are a semiconductor device and a method of fabricating a semiconductor device. The method includes providing a substrate having a channel region; forming a gate structure, which comprises a dummy gate pattern, on the substrate; forming first and second trenches by recessing the substrate on both sides of the gate structure, respectively; forming a first semiconductor pattern in the first and second trenches; removing the dummy gate pattern to expose a portion of the channel region; forming a recessed channel region by recessing the portion of the channel region; and forming a second semiconductor pattern in the recessed region.
    Type: Application
    Filed: September 23, 2011
    Publication date: May 31, 2012
    Inventors: Hyun-Jung Lee, Young-Pil Kim, Jin-Bum Kim, Sang-Bom Kang, Kwan-Yong Lim
  • Publication number: 20120108023
    Abstract: A semiconductor device is formed with a gate pattern formed on a substrate, and a recrystallized region having a stacking fault defect in the substrate at one side of the gate pattern. The semiconductor device can have a reduced leakage current and improved channel conductivity.
    Type: Application
    Filed: September 22, 2011
    Publication date: May 3, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwan-Yong Lim, Chung-Geun Koh, Sang-Bom Kang, Ui-Hui Kwon, Hyun-Jung Lee, Tae-Ouk Kwon, Seok-Hoon Kim
  • Publication number: 20120034749
    Abstract: A method of manufacturing a semiconductor device can be provided by forming a gate structure on a substrate and forming a diffusion barrier layer on the gate structure and the substrate, A stress layer can be formed on the diffusion barrier layer comprising a metal nitride or a metal oxide having a concentration of nitrogen or oxygen associated therewith. The stress layer can be heated to transform the stress layer into a tensile stress layer to reduce the concentration of the nitrogen or the oxygen in the stress layer. The tensile stress layer and the diffusion barrier layer can be removed.
    Type: Application
    Filed: August 3, 2011
    Publication date: February 9, 2012
    Inventors: Kwan-Yong LIM, Chung-Geun Koh, Hyun-Jung Lee, Tae-Ouk Kwon, Seok-Hoon Kim, Tae-Ho Cha
  • Patent number: 8101480
    Abstract: A method of forming a transistor induces stress in the channel region using a stress memorization technique (SMT). Impurities are implanted into a substrate adjacent a gate electrode structure to produce an amorphous region adjacent the channel region. The amorphous region is then recrystallized by forming a metal-oxide layer over the amorphous region, and then thermally treating the same. The crystallization creates compressive stress in the amorphous region. As a result, stress is induced in the channel region of the substrate located under the gate electrode structure.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: January 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Hoon Kim, Chung-Geun Koh, Kwan-Yong Lim, Hyun-Jung Lee, Tae-Ouk Kwon, Sang-Bom Kang
  • Publication number: 20120012928
    Abstract: A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 19, 2012
    Inventors: Kwan-Yong Lim, Hong-Seon Yang, Dong-Sun Sheen, Se-Aug Jang, Heung-Jae Cho, Yong-Soo Kim, Min-Gyu Sung, Tae-Yoon Kim
  • Publication number: 20120007246
    Abstract: A semiconductor device includes a substrate, a pattern including a conductive layer and a hard mask layer stacked over the substrate, a capping layer surrounding sidewalls of the pattern, and a stress buffer layer disposed between the hard mask layer and the capping layer. The stress buffer layer is configured to inhibit transfer of stress between the hard mask layer and the capping layer during a thermal process so as to inhibit leaning of the capping layer.
    Type: Application
    Filed: September 20, 2011
    Publication date: January 12, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventors: Min-Gyu SUNG, Heung-Jae Cho, Kwan-Yong Lim
  • Publication number: 20110278657
    Abstract: An apparatus, system, and method for a capacitance change non-volatile memory device. The apparatus may include a substrate, a source region in the substrate, a drain region in the substrate, a tunnel oxide layer on the substrate substantially between the source region and the drain region, a floating gate layer on the tunnel oxide layer, a resistance changing material layer on the floating gate layer, and a control gate on the resistance changing material layer.
    Type: Application
    Filed: May 11, 2010
    Publication date: November 17, 2011
    Inventors: Kwan-Yong Lim, Chanro Park, Hokyung Park, Paul Kirsch
  • Patent number: 8053841
    Abstract: A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and having a work function ranging from approximately 4.4 eV to approximately 4.8 eV.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: November 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Se-Aug Jang, Heung-Jae Cho, Kwan-Yong Lim, Tae-Yoon Kim