Patents by Inventor Kwang Hong

Kwang Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200388501
    Abstract: Disclosed is a method of reducing surface unevenness of a semiconductor wafer (100). In a preferred embodiment, the method comprises: removing a portion of a deposited layer and a protective layer thereon using a first slurry to provide an intermediate surface (1123). In the described embodiment, the deposited layer includes an epitaxial layer (112) and the protective layer includes a first dielectric layer (113). The first slurry includes particles with a hardness level the same as or exceeding that of the epitaxial layer (112). A slurry for use in wafer fabrication for reducing surface unevenness of a semiconductor wafer is also disclosed.
    Type: Application
    Filed: February 19, 2019
    Publication date: December 10, 2020
    Applicants: Massachusetts Institute of Technology, Nanyang Technological University, National University of Singapore
    Inventors: Li Zhang, Kwang Hong Lee, Keith Cheng Yeow Ng, Kenneth Eng Kian Lee, Eugene A. Fitzgerald, Soo Jin Chua, Chuan Seng Tan
  • Patent number: 10847553
    Abstract: A method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display is provided. The method comprising providing a first wafer comprising first layers disposed over a first substrate, said first layers comprising non-silicon based semiconductor material for forming p-n junction LEDs (light emitting devices); providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate, said CMOS devices for controlling the LEDs; and bonding the first and second wafers to form a composite wafer via a double-bonding transfer process.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 24, 2020
    Assignees: Massachusetts Institute of Technology, Nanyang Technological University, National University of Singapore
    Inventors: Li Zhang, Eng Kian Kenneth Lee, Soo Jin Chua, Eugene A. Fitzgerald, Siau Ben Chiah, Joseph Sylvester Chang, Yong Qu, Wei Shu, Kwang Hong Lee, Bing Wang
  • Publication number: 20200345288
    Abstract: The present invention relates to an eye movement measurement method including the steps of: (a) presenting standardized nystagmus test items and receiving am image of an eye in accordance with the standardized nystagmus test items; (b) recognizing a pupil and an iris from the image of the eye; (c) calculating amounts of horizontal and vertical changes of the pupil and an amount of torsional movement of the iris; (d) determining change values and orientations for three axis directions of the eye on the basis of the amounts of the horizontal and vertical changes of the pupil and the amount of the torsional movement of the iris; and (e) generating a diagnosis result for vertigo through deep learning modeling on the basis of the change values and orientations of the three axis directions of the eye.
    Type: Application
    Filed: April 26, 2018
    Publication date: November 5, 2020
    Applicant: Industry Academic Cooperation Foundation, Hallym University
    Inventors: Sung Kwang Hong, Eun Cheon Lim, Jeong Hye Park
  • Patent number: 10748845
    Abstract: Various applications of interconnect substrates in power management systems are described.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: August 18, 2020
    Assignee: Volterra Semiconductor Corporation
    Inventors: Mihalis Michael, Kwang Hong Tan, Ilija Jergovic, Chiteh Chiang, Anthony Stratakos
  • Patent number: 10672608
    Abstract: A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: June 2, 2020
    Assignees: Massachusetts Institute of Technology, National University of Singapore, Nanyang Technological University
    Inventors: Kwang Hong Lee, Li Zhang, Soo Jin Chua, Eng Kian Kenneth Lee, Eugene A. Fitzgerald, Chuan Seng Tan
  • Patent number: 10598853
    Abstract: Various embodiments may provide an optical structure. The optical structure may include a substrate. The optical structure may also include a core layer configured to carry optical light. The core layer may include germanium. The optical structure may further include an intermediate layer separating the substrate and the core layer so that the substrate is isolated from the core layer. The intermediate layer may include one or more materials selected from a group consisting of III-V materials, dielectric materials, and chalcogenide materials. A width of the core layer may be smaller than a width of the intermediate layer. A refractive index of the core layer may be more than 4. A refractive index of the intermediate layer may be smaller than 3.6.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: March 24, 2020
    Assignees: NANYANG TECHNOLOGICAL UNIVERSITY, MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Chuan Seng Tan, Wei Li, P Anantha, Kwang Hong Lee, Shuyu Bao, Lin Zhang
  • Patent number: 10548916
    Abstract: The present invention relates to a composition for prevention or treatment of sepsis or septic shock, in which the composition includes neoagarooligosaccharide as an active ingredient, and the neoagarooligosaccharide according to the present invention has an excellent effect in terms of immune enhancement by effectively suppressing inflammation, and also exhibits a good effect in preventing sepsis, and therefore can be effectively used in pharmaceuticals and functional foods for prevention or treatment of sepsis or septic shock and immune enhancement.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: February 4, 2020
    Assignee: DYNEBIO INC.
    Inventors: Je Hyeon Lee, Moon Hee Lee, Sun Joo Hong, Soon Kwang Hong
  • Patent number: 10510560
    Abstract: A method of encapsulating a substrate is disclosed, in which the substrate has at least the following layers: a CMOS device layer, a layer of first semiconductor material different to silicon, and a layer of second semiconductor material, the layer of first semiconductor material arranged intermediate the CMOS device layer and the layer of second semiconductor material. The method comprises: (i) circumferentially removing a portion of the substrate at the edges; and (ii) depositing a dielectric material on the substrate to replace the portion removed at step (i) for encapsulating at least the CMOS device layer and the layer of first semiconductor material. A related substrate is also disclosed.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: December 17, 2019
    Assignees: Nanyang Technological University, Massachusetts Institute of Technology
    Inventors: Kwang Hong Lee, Eng Kian Kenneth Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Viet Cuong Nguyen
  • Publication number: 20190355766
    Abstract: A method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display is provided. The method comprising providing a first wafer comprising first layers disposed over a first substrate, said first layers comprising non-silicon based semiconductor material for forming p-n junction LEDs (light emitting devices); providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate, said CMOS devices for controlling the LEDs; and bonding the first and second wafers to form a composite wafer via a double-bonding transfer process.
    Type: Application
    Filed: January 12, 2018
    Publication date: November 21, 2019
    Inventors: Li ZHANG, Eng Kian, Kenneth LEE, Soo Jin CHUA, Eugene A. FITZGERALD, Siau Ben CHIAH, Joseph Sylvester CHANG, Yong QU, Wei SHU, Kwang Hong LEE, Bing WANG
  • Patent number: 10483351
    Abstract: A method of manufacturing a substrate with reduced threading dislocation density is disclosed, which comprises: (i) at a first temperature, forming a first layer of wafer material on a semiconductor substrate, the first layer arranged to be doped with a first concentration of at least one dopant that is different to the wafer material; and (ii) at a second temperature higher than the first temperature, forming a second layer of the wafer material on the first layer to obtain the substrate, the second layer arranged to be doped with a progressively decreasing concentration of the dopant during formation, the doping configured to be decreased from the first concentration to a second concentration. The wafer material and dopant are different to silicon. A related substrate is also disclosed.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: November 19, 2019
    Assignees: Nanyang Technological University, Massachusetts Institute of Technology
    Inventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Shuyu Bao
  • Publication number: 20190341344
    Abstract: Various applications of interconnect substrates in power management systems are described.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 7, 2019
    Inventors: Mihalis Michael, Kwang Hong Tan, Ilija Jergovic, Chiteh Chiang, Anthony Stratakos
  • Publication number: 20190290678
    Abstract: The present invention relates to a composition for prevention or treatment of sepsis or septic shock, in which the composition includes neoagarooligosaccharide as an active ingredient, and the neoagarooligosaccharide according to the present invention has an excellent effect in terms of immune enhancement by effectively suppressing inflammation, and also exhibits a good effect in preventing sepsis, and therefore can be effectively used in pharmaceuticals and functional foods for prevention or treatment of sepsis or septic shock and immune enhancement.
    Type: Application
    Filed: April 12, 2019
    Publication date: September 26, 2019
    Inventors: Je Hyeon Lee, Moon Hee Lee, Sun Joo Hong, Soon Kwang Hong
  • Patent number: 10418273
    Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed, comprising: (i) doping a first portion of a germanium layer with a first dopant to form a first electrode, the germanium layer arranged with a first semiconductor substrate; (ii) forming at least one layer of dielectric material adjacent to the first electrode to obtain a combined substrate; (iii) bonding a second semiconductor substrate to the layer of dielectric material and removing the first semiconductor substrate from the combined substrate to expose a second portion of the germanium layer with misfit dislocations; (iv) removing the second portion of the germanium layer to enable removal of the misfit dislocations and to expose a third portion of the germanium layer; and (v) doping the third portion of the germanium layer with a second dopant to form a second electrode. The electrodes are separated from each other by the germanium layer, and the first dopant is different to the second dopant.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: September 17, 2019
    Assignees: Nanyang Technological University, Massachusetts Institute of Technology
    Inventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Shuyu Bao, Yiding Lin, Jurgen Michel
  • Patent number: 10332827
    Abstract: Various applications of interconnect substrates in power management systems are described.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: June 25, 2019
    Assignee: Volterra Semiconductor Corporation
    Inventors: Mihalis Michael, Kwang Hong Tan, Ilija Jergovic, Chiteh Chiang, Anthony J. Stratakos
  • Patent number: 10290785
    Abstract: A laminating structure of an electronic device using a transferring element according to the present disclosure includes a target substrate, a bottom electrode formed on the target substrate, an electronic device which is bonded to the bottom electrode, a top contact formed on the electronic device, a transferring element which is placed between the bottom electrode and the electronic device on the target substrate, and a top electrode connected to the electronic device, wherein the transferring element attached to the carrier substrate comes into contact with the electronic device, and is then transferred onto the target substrate.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: May 14, 2019
    Assignee: CENTER FOR INTEGRATED SMART SENSORS FOUNDATION
    Inventors: Keon Jae Lee, Han Eol Lee, Do Hyun Kim, Jung Ho Shin, Seong Kwang Hong
  • Publication number: 20190103532
    Abstract: A laminating structure of an electronic device using a transferring element according to the present disclosure includes a target substrate, a bottom electrode formed on the target substrate, an electronic device which is bonded to the bottom electrode, a top contact formed on the electronic device, a transferring element which is placed between the bottom electrode and the electronic device on the target substrate, and a top electrode connected to the electronic device, wherein the transferring element attached to the carrier substrate comes into contact with the electronic device, and is then transferred onto the target substrate.
    Type: Application
    Filed: October 3, 2017
    Publication date: April 4, 2019
    Inventors: Keon Jae Lee, Han Eol Lee, Do Hyun Kim, Jung Ho Shin, Seong Kwang Hong
  • Publication number: 20190074214
    Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed, comprising: (i) doping a first portion of a germanium layer with a first dopant to form a first electrode, the germanium layer arranged with a first semiconductor substrate; (ii) forming at least one layer of dielectric material adjacent to the first electrode to obtain a combined substrate; (iii) bonding a second semiconductor substrate to the layer of dielectric material and removing the first semiconductor substrate from the combined substrate to expose a second portion of the germanium layer with misfit dislocations; (iv) removing the second portion of the germanium layer to enable removal of the misfit dislocations and to expose a third portion of the germanium layer; and (v) doping the third portion of the germanium layer with a second dopant to form a second electrode. The electrodes are separated from each other by the germanium layer, and the first dopant is different to the second dopant.
    Type: Application
    Filed: October 11, 2016
    Publication date: March 7, 2019
    Applicants: Nanyang Technological University, Massachusetts Institute of Technology
    Inventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Shuyu Bao, Yiding Lin, Jurgen Michel
  • Publication number: 20190051516
    Abstract: A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.
    Type: Application
    Filed: January 20, 2017
    Publication date: February 14, 2019
    Inventors: Kwang Hong Lee, Li Zhang, Soo Jin Chua, Eng Kian Kenneth Lee, Eugene A. Fitzgerald, Chuan Seng Tan
  • Publication number: 20190035628
    Abstract: Method and structure for reducing substrate fragility. In one embodiment, a substrate for metamorphic epitaxy of a material film is provided, the substrate comprising a passivation layer defining a growth window for the material film on a deposition surface of the substrate, the growth window being laterally spaced from an edge of the substrate.
    Type: Application
    Filed: January 19, 2017
    Publication date: January 31, 2019
    Applicants: MASSACHUSETTS INSTITUTE OF TECHNOLOGY, NATIONAL UNIVERSITY OF SINGAPORE, NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Li ZHANG, Kwang Hong LEE, Shuyu BAO, Eng Kian Kenneth LEE, Eugene A. FITZGERALD, Soo Jin CHUA, Chuan Seng TAN
  • Publication number: 20190033523
    Abstract: Various embodiments may provide an optical structure. The optical structure may include a substrate. The optical structure may also include a core layer configured to carry optical light. The core layer may include germanium. The optical structure may further include an intermediate layer separating the substrate and the core layer so that the substrate is isolated from the core layer. The intermediate layer may include one or more materials selected from a group consisting of III-V materials, dielectric materials, and chalcogenide materials. A width of the core layer may be smaller than a width of the intermediate layer. A refractive index of the core layer may be more than 4. A refractive index of the intermediate layer may be smaller than 3.6.
    Type: Application
    Filed: February 10, 2017
    Publication date: January 31, 2019
    Applicants: NANYANG TECHNOLOGICAL UNIVERSITY, MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Chuan Seng TAN, Wei LI, P ANANTHA, Kwang Hong LEE, Shuyu BAO, Lin ZHANG