Patents by Inventor Kwang Myoung Rho
Kwang Myoung Rho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230378135Abstract: A stacked integrated circuit includes a first chip including a first area and a second area that are disposed to be substantially symmetrical to each other in relation to a first rotating axis. The first area includes a first through via set and a first front pad set that are connected by using a first connection method. The second area includes a second through via set and a second front pad set that are connected by using a second connection method. The first through via set and the second through via set are disposed to be substantially symmetrical to each other in relation to the first rotating axis. The first front pad set and the second front pad set are disposed to be substantially symmetrical to each other in relation to the first rotating axis.Type: ApplicationFiled: October 31, 2022Publication date: November 23, 2023Applicant: SK hynix Inc.Inventors: Dong Uk LEE, Kwang Myoung RHO, Choung Ki SONG, Seung Han OAK, Woo Yeong CHO
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Patent number: 10490274Abstract: The semiconductor memory includes a plurality of word lines; and a plurality of columns including a plurality of resistive storage cells corresponding to the plurality of word lines, the plurality of columns being divided into a plurality of pages each having one or more columns; a memory circuit coupled to the semiconductor memory to sense data stored in the resistive storage cells; and a memory control circuit coupled to the semiconductor memory and the memory circuit to control sensing of the stored data by the memory circuit to, in a read operation, sense data of resistive storage cells included in a selected page by continuously active-precharging one or more word lines among the plurality of word lines in a period in which the selected page among the plurality of pages is activated.Type: GrantFiled: August 27, 2018Date of Patent: November 26, 2019Assignee: SK hynix Inc.Inventor: Kwang-Myoung Rho
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Publication number: 20180366190Abstract: The semiconductor memory includes a plurality of word lines; and a plurality of columns including a plurality of resistive storage cells corresponding to the plurality of word lines, the plurality of columns being divided into a plurality of pages each having one or more columns; a memory circuit coupled to the semiconductor memory to sense data stored in the resistive storage cells; and a memory control circuit coupled to the semiconductor memory and the memory circuit to control sensing of the stored data by the memory circuit to, in a read operation, sense data of resistive storage cells included in a selected page by continuously active-precharging one or more word lines among the plurality of word lines in a period in which the selected page among the plurality of pages is activated.Type: ApplicationFiled: August 27, 2018Publication date: December 20, 2018Inventor: Kwang-Myoung Rho
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Patent number: 10121537Abstract: An electronic device includes a semiconductor memory that includes: resistive storage cells; a reference resistance cell; a comparison block electrically coupled to the resistive storage cells and the reference resistance cell through first and second input terminals, to compare a cell current flowing through the first input terminal and a reference current flowing through the second input terminal; a first clamp part to control a maximum current amount of the cell current depending on a voltage level of a first node; a second clamp part to control a maximum current amount of the reference current depending on the voltage level of the first node; a voltage stabilization block to stabilize a voltage of the first node during a charging or a discharging period; and a switching part electrically coupled with the first node and the voltage stabilization block in the charging period or the discharging period.Type: GrantFiled: September 14, 2017Date of Patent: November 6, 2018Assignee: SK hynix Inc.Inventor: Kwang-Myoung Rho
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Patent number: 10062436Abstract: The semiconductor memory includes a plurality of word lines; and a plurality of columns including a plurality of resistive storage cells corresponding to the plurality of word lines, the plurality of columns being divided into a plurality of pages each having one or more columns; a memory circuit coupled to the semiconductor memory to sense data stored in the resistive storage cells; and a memory control circuit coupled to the semiconductor memory and the memory circuit to control sensing of the stored data by the memory circuit to, in a read operation, sense data of resistive storage cells included in a selected page by continuously active-precharging one or more word lines among the plurality of word lines in a period in which the selected page among the plurality of pages is activated.Type: GrantFiled: October 12, 2016Date of Patent: August 28, 2018Assignee: SK hynix Inc.Inventor: Kwang-Myoung Rho
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Publication number: 20180158523Abstract: An electronic device includes a semiconductor memory that includes: resistive storage cells; a reference resistance cell; a comparison block electrically coupled to the resistive storage cells and the reference resistance cell through first and second input terminals, to compare a cell current flowing through the first input terminal and a reference current flowing through the second input terminal; a first clamp part to control a maximum current amount of the cell current depending on a voltage level of a first node; a second clamp part to control a maximum current amount of the reference current depending on the voltage level of the first node; a voltage stabilization block to stabilize a voltage of the first node during a charging or a discharging period; and a switching part electrically coupled with the first node and the voltage stabilization block in the charging period or the discharging period.Type: ApplicationFiled: September 14, 2017Publication date: June 7, 2018Inventor: Kwang-Myoung Rho
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Publication number: 20170236568Abstract: The semiconductor memory includes a plurality of word lines; and a plurality of columns including a plurality of resistive storage cells corresponding to the plurality of word lines, the plurality of columns being divided into a plurality of pages each having one or more columns; a memory circuit coupled to the semiconductor memory to sense data stored in the resistive storage cells; and a memory control circuit coupled to the semiconductor memory and the memory circuit to control sensing of the stored data by the memory circuit to, in a read operation, sense data of resistive storage cells included in a selected page by continuously active-precharging one or more word lines among the plurality of word lines in a period in which the selected page among the plurality of pages is activated.Type: ApplicationFiled: October 12, 2016Publication date: August 17, 2017Inventor: Kwang-Myoung Rho
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Patent number: 9105331Abstract: A semiconductor memory apparatus includes a resistive memory cell coupled between a bit line and a bit line bar; a control unit configured to couple the bit line to a first node and apply a reference voltage to a second node in response to a first sense amplifier enable signal and a second sense amplifier enable signal; a data output sense amplifier configured to sense and amplify a voltage of the first node and a voltage of the second node; a data transfer unit configured to couple the first and second nodes to a data line and a data line bar in response to a column select signal; and a data input unit configured to drive the bit line and the bit line bar according to voltage levels of the first and second nodes in response to a write enable signal.Type: GrantFiled: March 18, 2013Date of Patent: August 11, 2015Assignee: SK Hynix Inc.Inventor: Kwang Myoung Rho
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Patent number: 8811059Abstract: Provided is a resistive memory apparatus including a plurality of memory areas each including a main memory cell array coupled to a plurality of word lines and a reference cell array coupled to a plurality of reference word lines. Each of the memory areas shares a bit line driver/sinker with an adjacent memory area.Type: GrantFiled: December 28, 2011Date of Patent: August 19, 2014Assignee: SK Hynix Inc.Inventor: Kwang Myoung Rho
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Publication number: 20140098621Abstract: A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.Type: ApplicationFiled: December 9, 2013Publication date: April 10, 2014Applicant: 658868 N.B. Inc.Inventors: Young-Hoon OH, Kwang-Myoung RHO
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Publication number: 20140003129Abstract: A semiconductor memory apparatus includes a resistive memory cell coupled between a bit line and a bit line bar; a control unit configured to couple the bit line to a first node and apply a reference voltage to a second node in response to a first sense amplifier enable signal and a second sense amplifier enable signal; a data output sense amplifier configured to sense and amplify a voltage of the first node and a voltage of the second node; a data transfer unit configured to couple the first and second nodes to a data line and a data line bar in response to a column select signal; and a data input unit configured to drive the bit line and the bit line bar according to voltage levels of the first and second nodes in response to a write enable signal.Type: ApplicationFiled: March 18, 2013Publication date: January 2, 2014Applicant: SK HYNIX INC.Inventor: Kwang Myoung RHO
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Publication number: 20130094277Abstract: Provided is a resistive memory apparatus including a plurality of memory areas each including a main memory cell array coupled to a plurality of word lines and a reference cell array coupled to a plurality of reference word lines. Each of the memory areas shares a bit line driver/sinker with an adjacent memory area.Type: ApplicationFiled: December 28, 2011Publication date: April 18, 2013Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Kwang Myoung RHO
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Patent number: 8400824Abstract: A non-volatile memory and method for controlling the same prevents a faulty operation from being generated in a read operation, resulting in increase in operation reliability. The non-volatile memory device includes a cell array configured to include a plurality of unit cells in which a read or write operation of data is achieved in a unit cell in response to a variation of resistance, a reference cell array configured to include a plurality of reference cells, each of which has the same structure as that of the unit cell, a global reference current generation circuit configured to generate a global reference current corresponding to a position of the reference cell so as to verify data stored in the reference cell array, and a sense-amplifier configured to compare a current flowing in the reference cell array with the global reference current during a write verification operation of the reference cell array, and thus sense data.Type: GrantFiled: December 28, 2010Date of Patent: March 19, 2013Assignee: Hynix Semiconductor Inc.Inventor: Kwang Myoung Rho
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Patent number: 8225417Abstract: A circuit for controlling a signal line transmitting data. The circuit includes a data level controller that, when the level of the data transmitted through the signal line is changed, controls the level of the data to be lower than an external power supply voltage level and higher than a ground voltage level after a predetermined time.Type: GrantFiled: July 9, 2008Date of Patent: July 17, 2012Assignee: SK hynix, Inc.Inventors: Kwang-Myoung Rho, Jae-Jin Lee
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Publication number: 20120147664Abstract: A non-volatile memory and method for controlling the same prevents a faulty operation from being generated in a read operation, resulting in increase in operation reliability. The non-volatile memory device includes a cell array configured to include a plurality of unit cells in which a read or write operation of data is achieved in a unit cell in response to a variation of resistance, a reference cell array configured to include a plurality of reference cells, each of which has the same structure as that of the unit cell, a global reference current generation circuit configured to generate a global reference current corresponding to a position of the reference cell so as to verify data stored in the reference cell array, and a sense-amplifier configured to compare a current flowing in the reference cell array with the global reference current during a write verification operation of the reference cell array, and thus sense data.Type: ApplicationFiled: December 28, 2010Publication date: June 14, 2012Applicant: Hynix Semiconductor Inc.Inventor: Kwang Myoung RHO
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Patent number: 8106689Abstract: A power-up signal generating circuit of a semiconductor memory apparatus includes a current source unit configured to supply a current to a first node; a current sink unit configured to be turned on when the level of a divided voltage dividing an external voltage is equal to or higher than a predetermined level to allow the current to flow from a first node to a second node; a control unit configured to control the turn-on timing of the current sink unit by controlling a voltage level of the second node; and a signal generating unit configured to enable a power-up signal depending on a voltage level of the first node.Type: GrantFiled: May 26, 2011Date of Patent: January 31, 2012Assignee: Hynix Semiconductor Inc.Inventor: Kwang-Myoung Rho
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Patent number: 8036026Abstract: A semiconductor memory device includes a plurality of memory cells configured to store data having a polarity corresponding to a direction of current flowing through a source line and a bit line; and a precharge driving unit configured to precharge the bit line to a voltage corresponding to the data in response to a precharging signal before the data are stored in the memory cells.Type: GrantFiled: June 19, 2009Date of Patent: October 11, 2011Assignee: Hynix Semiconductor Inc.Inventors: Kwang-Myoung Rho, Woo-Hyun Seo
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Publication number: 20110221484Abstract: A power-up signal generating circuit of a semiconductor memory apparatus includes a current source unit configured to supply a current to a first node; a current sink unit configured to be turned on when the level of a divided voltage dividing an external voltage is equal to or higher than a predetermined level to allow the current to flow from a first node to a second node; a control unit configured to control the turn-on timing of the current sink unit by controlling a voltage level of the second node; and a signal generating unit configured to enable a power-up signal depending on a voltage level of the first node.Type: ApplicationFiled: May 26, 2011Publication date: September 15, 2011Applicant: Hynix Semiconductor Inc.Inventor: KWANG MYOUNG RHO
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Patent number: RE44632Abstract: A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.Type: GrantFiled: June 29, 2012Date of Patent: December 10, 2013Assignee: 658868 N.B. Inc.Inventors: Young-Hoon Oh, Kwang-Myoung Rho
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Patent number: RE48341Abstract: A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.Type: GrantFiled: December 9, 2013Date of Patent: December 1, 2020Assignee: Conversant Intellectual Property Management Inc.Inventors: Young-Hoon Oh, Kwang-Myoung Rho