Abstract: A redundancy data storage circuit of a semiconductor memory includes a memory cell array; a write driver configured to write redundancy data in the memory cell array in response to a test signal; and a sense amplifier configured to detect and output the redundancy data written in the memory cell array in response to a read signal.

Abstract: A power-up signal generating circuit of a semiconductor memory apparatus includes a current source unit configured to supply a current to a first node; a current sink unit configured to be turned on when the level of a divided voltage dividing an external voltage is equal to or higher than a predetermined level to allow the current to flow from a first node to a second node; a control unit configured to control the turn-on timing of the current sink unit by controlling a voltage level of the second node; and a signal generating unit configured to enable a power-up signal depending on a voltage level of the first node.

Abstract: A semiconductor memory cell includes a plurality of memory cells configured to store data having polarity corresponding to a direction of current flowing in first and second driving lines, a current generator configured to generate a predetermined read current, apply the predetermined read current to the plurality of memory cells, and generate a data current corresponding variation of the read current according to the data and a current controller connected to a current path of the read current and configured to control a current amount of the read current.

Abstract: A bulk voltage detector comprises a voltage sensor configured to receive a bulk voltage and compare the received bulk voltage with a target level to provide a first detection signal having a voltage gain that is increased within a predetermined voltage range around the target level, and an amplifier coupled with the voltage sensor, the amplifier configured to receive the first detection signal and invert and amplify the first detection signal.

Abstract: A semiconductor memory cell includes a plurality of memory cells configured to store data having polarity corresponding to a direction of current flowing in first and second driving lines, a current generator configured to generate a predetermined read current, apply the predetermined read current to the plurality of memory cells, and generate a data current corresponding variation of the read current according to the data and a current controller connected to a current path of the read current and configured to control a current amount of the read current.

Abstract: A semiconductor memory device includes a plurality of memory cells configured to store data having a polarity corresponding to a direction of current flowing through a source line and a bit line; and a precharge driving unit configured to precharge the bit line to a voltage corresponding to the data in response to a precharging signal before the data are stored in the memory cells.

Abstract: A power-up signal generating circuit of a semiconductor memory apparatus includes a current source unit configured to supply a current to a first node; a current sink unit configured to be turned on when the level of a divided voltage dividing an external voltage is equal to or higher than a predetermined level to allow the current to flow from a first node to a second node; a control unit configured to control the turn-on timing of the current sink unit by controlling a voltage level of the second node; and a signal generating unit configured to enable a power-up signal depending on a voltage level of the first node.

Abstract: A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.

Abstract: A delay circuit that includes a logic gate through which an input signal passes, a capacitor configured to be charged and discharged at an output terminal of the logic gate and delaying the input signal, and a mirroring unit configured to constantly maintain current output by the logic gate by mirroring current output by a constant current source.

Abstract: An output driver for use in a semiconductor memory device includes a pull-up metal oxide semiconductor (MOS) transistor for pulling-up a voltage loaded on an output node in response to a pull-up control signal; a pull-up linear element connected between the pull-up MOS transistor and the output node for increasing a linearity of an output current; a pull-down MOS transistor for pulling-down the voltage loaded on the output node in response to a pull-down control signal; and a pull-down linear element connected between the pull-down MOS transistor and the output node for increasing the linearity of the output current, wherein the pull-up MOS transistor and the pull-up linear element are different typed MOS transistors and the pull-down MOS transistor and the pull-down linear element are different typed MOS transistors.

Abstract: A delay circuit that includes a logic gate through which an input signal passes, a capacitor configured to be charged and discharged at an output terminal of the logic gate and delaying the input signal, and a mirroring unit configured to constantly maintain current output by the logic gate by mirroring current output by a constant current source.

Abstract: An offset voltage measuring apparatus includes an offset voltage measuring unit including a plurality of measurement nodes having a current variation in response to a feedback voltage. An offset voltage amplifying unit outputs an output voltage amplified in response to an output signal of the offset voltage measuring unit, changes feedback voltage in response to a change in the output voltage and feeds back the feedback voltage to the offset voltage measuring unit.

Abstract: A power-up circuit that can reduce a variation of the triggering voltage that is caused by variations in process or temperature in a semiconductor integrated circuit is described. The power-up circuit includes a first detector for outputting a first triggering voltage signal according to a power voltage level and a second detector for outputting a second triggering voltage signal according to the power voltage level. The power-up circuit also includes an output unit generating and outputting a power-up signal according to the first triggering voltage signal and the second triggering voltage signal and providing the output to various internal circuits.

Abstract: A power-up circuit for reducing a variation in triggering voltage in a semiconductor integrated circuit is described. The power-up circuit includes a pull-up resistor unit that is connected to a power voltage source. A pull-up resistance adjusting unit varies the resistance value of the pull-up resistor unit. The power-up circuit also includes a pull-down resistor unit that is connected between the pull-up resistor unit and a ground. Finally, the power-up circuit includes a detector connected to a common node of the pull-up resistor unit and the pull-down resistor unit.

Abstract: A bulk voltage detector comprises a voltage sensor configured to receive a bulk voltage and compare the received bulk voltage with a target level to provide a first detection signal having a voltage gain that is increased within a predetermined voltage range around the target level, and an amplifier coupled with the voltage sensor, the amplifier configured to receive the first detection signal and invert and amplify the first detection signal.

Abstract: A circuit for controlling a signal line transmitting data. The circuit includes a data level controller that, when the level of the data transmitted through the signal line is changed, controls the level of the data to be lower than an external power supply voltage level and higher than a ground voltage level after a predetermined time.

Abstract: A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.

Abstract: A delay circuit controls a delay time according to variation of a power supply voltage. In the delay circuit, the capacitance of a capacitor connected in parallel to the delay line is changed according to the change of the power supply voltage. Alternatively, a current is made to flow through one path selected from a plurality of paths having different resistance between the input and the output of the delay line. Accordingly, the delay time can be independently controlled or adjusted by greatly changing the time taken to pass through the delay line according to the change of the power supply voltage.

Abstract: An output driver includes a pre-pull up drive unit configured to perform a pre-pull up drive operation; a pre-pull down drive unit configured to perform a pre-pull down drive operation; a drive unit configured to perform a drive operation in response to outputs of the pre-pull up drive unit and the pre-pull down drive unit; and a compensation unit configured to sense changes of driving strengths of the pre-pull up drive unit and the pre-pull down drive unit to control the driving forces of the pre-pull up drive unit and the pre-pull down drive unit.

Abstract: A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.