Abstract: A data output driver circuit can be configured to comprise a predriver control unit generate a plurality of pullup output load control signals and a plurality of pulldown output load control signals depending upon a sensed external voltage, and a predriver is configured to output a signal by adjusting a slew rate of an inputted data in response to the plurality of pullup output load control signals and the plurality of pulldown output load control signals.

Abstract: An offset voltage measuring apparatus includes an offset voltage measuring unit including a plurality of measurement nodes having a current variation in response to a feedback voltage. An offset voltage amplifying unit outputs an output voltage amplified in response to an output signal of the offset voltage measuring unit, changes feedback voltage in response to a change in the output voltage and feeds back the feedback voltage to the offset voltage measuring unit.

Abstract: A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.

Abstract: An output driver includes a pre-pull up drive unit configured to perform a pre-pull up drive operation; a pre-pull down drive unit configured to perform a pre-pull down drive operation; a drive unit configured to perform a drive operation in response to outputs of the pre-pull up drive unit and the pre-pull down drive unit; and a compensation unit configured to sense changes of driving strengths of the pre-pull up drive unit and the pre-pull down drive unit to control the driving forces of the pre-pull up drive unit and the pre-pull down drive unit.

Abstract: A delay circuit controls a delay time according to variation of a power supply voltage. In the delay circuit, the capacitance of a capacitor connected in parallel to the delay line is changed according to the change of the power supply voltage. Alternatively, a current is made to flow through one path selected from a plurality of paths having different resistance between the input and the output of the delay line. Accordingly, the delay time can be independently controlled or adjusted by greatly changing the time taken to pass through the delay line according to the change of the power supply voltage.

Abstract: An ESD protection circuit includes: a first metal oxide semiconductor (MOS) transistor discharging an excessive electrostatic current generated between an input pad and an internal circuit, and having a first terminal connected to a ground voltage supply terminal; and a second MOS transistor discharging an electrostatic current generated between the input pad and the internal circuit, and having a gate and a first terminal connected to a bulk terminal of the first MOS transistor. The first terminal is connected to the ground voltage supply terminal through an interconnection line having a parasitic resistance with a predetermined value.

Abstract: A bit-line sense amplifier is disclosed that includes switching elements to sequentially modify the sense amplifier to a negative feedback differential amplifier, a normal differential amplifier, a positive feedback differential amplifier, and a cross-coupled latch, in that order. The sense amplifier sensing data on a pair of bit-lines in a semiconductor memory; and a transistor is connected between one of the differential amplifiers and a common current source. The transistor has a resistance which is variable depending on a potential of an output of one of the differential amplifiers or remains constant by a different power source.

Abstract: An ESD protection circuit includes: a first metal oxide semiconductor (MOS) transistor discharging an excessive electrostatic current generated between an input pad and an internal circuit, and having a first terminal connected to a ground voltage supply terminal; and a second MOS transistor discharging an electrostatic current generated between the input pad and the internal circuit, and having a gate and a first terminal connected to a bulk terminal of the first MOS transistor. The first terminal is connected to the ground voltage supply terminal through an interconnection line having a parasitic resistance with a predetermined value.

Abstract: Disclosed is an output driver for a semiconductor device with an improved slew rate. The output driver comprises a first pre-driver receiving a first signal so as to output a second signal in which a slew rate is controlled, a second pre-driver receiving a third signal so as to output a fourth signal in which a slew rate is controlled, and a pull-up transistor and a pull-down transistor connected in series between a power supply voltage and a ground voltage. The pull-up transistor is turned on and/or off by the second signal, and the pull-down transistor is turned on and/or off by the fourth signal.

Abstract: A bit line sense amplifier for inhibiting increase of an offset voltage, and a method for fabricating the same are provided. The bit line sense amplifier comprises a plurality of CMOS inverters, which are cross-coupled corresponding to the paired bit lines. Each of the CMOS inverters senses and amplifies a voltage of the paired bit lines. Here, transistors comprised in each inverter are positioned at the same location in a well region where the transistors are formed. As a result, increase of the offset voltage due to inconsistency of electrical characteristics which results from difference in location of devices is inhibited, thereby improving sensitivity of the sense amplifier and characteristics of the DRAM.

Abstract: An output driver for use in a semiconductor memory device includes a pull-up metal oxide semiconductor (MOS) transistor for pulling-up a voltage loaded on an output node in response to a pull-up control signal; a pull-up linear element connected between the pull-up MOS transistor and the output node for increasing a linearity of an output current; a pull-down MOS transistor for pulling-down the voltage loaded on the output node in response to a pull-down control signal; and a pull-down linear element connected between the pull-down MOS transistor and the output node for increasing the linearity of the output current, wherein the pull-up MOS transistor and the pull-up linear element are different typed MOS transistors and the pull-down MOS transistor and the pull-down linear element are different typed MOS transistors.

Abstract: A bit line sense amplifier for inhibiting increase of an offset voltage, and a method for fabricating the same are provided. The bit line sense amplifier comprises a plurality of CMOS inverters, which are cross-coupled corresponding to the paired bit lines. Each of the CMOS inverters senses and amplifies a voltage of the paired bit lines. Here, transistors comprised in each inverter are positioned at the same location in a well region where the transistors are formed. As a result, increase of the offset voltage due to inconsistency of electrical characteristics which results from difference in location of devices is inhibited, thereby improving sensitivity of the sense amplifier and characteristics of the DRAM.

Abstract: Disclosed is an output driver for a semiconductor device with an improved slew rate. The output driver comprises a first pre-driver receiving a first signal so as to output a second signal in which a slew rate is controlled, a second pre-driver receiving a third signal so as to output a fourth signal in which a slew rate is controlled, and a pull-up transistor and a pull-down transistor connected in series between a power supply voltage and a ground voltage. The pull-up transistor is turned on and/or off by the second signal, and the pull-down transistor is turned on and/or off by the fourth signal.

Abstract: A semiconductor device having a shallow trench isolation structure, where the upper part of the trench is broader than the lower part of it, comprises an insulating layer on the sidewalls of the upper part of the trench, another insulating layer buried in the trench for isolating semiconductor devices and low-concentration doped regions near the upper part of the trench and high-concentration doped regions near the lower part of the trench. Therefore, the leakage current is prevented due to the sufficient amount of the ions in the high-concentration doped regions near the lower part of the trench and the narrow width effect is minimized owing to the insulating layer on the sidewalls of the upper part of the trench.

Abstract: The present invention provide a method for forming a triple well. The triple well includes an n-well, a first p-well surrounded with the n-well and a second p-well apart from the first p-well and adjacent to the n-well. According to the present invention, only one conductivity type of impurities are implanted in each well. Therefore, it is possible to prevent the decrease of the carrier mobility and increase of the leakage current.

Abstract: A semiconductor device having a shallow trench isolation structure, where the upper part of the trench is broader than the lower part of it, comprises an insulating layer on the sidewalls of the upper part of the trench, another insulating layer buried in the trench for isolating semiconductor devices and low-concentration doped regions near the upper part of the trench and high-concentration doped regions near the lower part of the trench. Therefore, the leakage current is prevented due to the sufficient amount of the ions in the high-concentration doped regions near the lower part of the trench and the narrow width effect is minimized owing to the insulating layer on the sidewalls of the upper part of the trench.

Abstract: A method for fabricating a semiconductor device having a buried channel structure, in which impurities having the same conductive type as a well are ion implanted, to increase the ion density beneath the buried channel, thereby enhancing the short channel characteristic and smooth on/off characteristic of MOSFET.

Abstract: A method for forming a transistor comprising the steps of: forming a trench in a substrate; filling an insulating layer in the lower portion of said trench except for the upper portion thereof; filling a conductive layer in the upper portion of said trench and on said insulating layer for a channel of the said transistor; forming a gate oxide layer on the resulting structure; and forming a gate electrode on said gate oxide layer; and implanting impurity ions into said substrate to form a source/drain region.

Abstract: A method of manufacturing a semiconductor device, capable of securing an alignment margin between bit lines and a storage node contact is disclosed herein.