Patents by Inventor Kwang-wook Lee
Kwang-wook Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10818522Abstract: Disclosed are a supercritical process chamber and an apparatus having the same. The process chamber includes a body frame having a protrusion protruding in an upward vertical direction from a first surface of the body frame and a recess defined by the protrusion and the first surface of the body frame; a cover frame; a buffer chamber arranged between the body frame and the cover frame; and a connector. The buffer chamber includes an inner vessel detachably coupled to the body frame providing a chamber space in the recess and an inner cover detachably coupled to the cover frame. The inner cover is in contact with a first surface of the inner vessel enclosing the chamber space from surroundings. The connector couples the body frame and the cover frame having the buffer chamber arranged therebetween such that the enclosed chamber space is transformed into a process space in which the supercritical process is performed.Type: GrantFiled: May 14, 2018Date of Patent: October 27, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Jine Park, Byung-Kwon Cho, Yong-Jhin Cho, Yong-Sun Ko, Yeon-Jin Gil, Kwang-Wook Lee
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Patent number: 10714499Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.Type: GrantFiled: June 25, 2019Date of Patent: July 14, 2020Assignee: SK hynix Inc.Inventors: Won Joon Choi, Min Sung Ko, Kyeong Bae Kim, Jong Gi Kim, Dong Sun Sheen, Jung Myoung Shim, Young Ho Yang, Hyeng Woo Eom, Kwang Wook Lee, Woo Jae Chung
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Publication number: 20190319045Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.Type: ApplicationFiled: June 25, 2019Publication date: October 17, 2019Inventors: Won Joon CHOI, Min Sung KO, Kyeong Bae KIM, Jong Gi KIM, Dong Sun SHEEN, Jung Myoung SHIM, Young Ho YANG, Hyeng Woo EOM, Kwang Wook LEE, Woo Jae CHUNG
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Patent number: 10438891Abstract: An integrated circuit device includes an insulating film on a substrate, a lower wiring layer penetrating at least a portion of the insulating film, the lower wiring layer including a first metal, a lower conductive barrier film surrounding a bottom surface and a sidewall of the lower wiring layer, the lower conductive barrier film including a second metal different from the first metal, a first metal silicide capping layer covering a top surface of the lower wiring layer, the first metal silicide capping layer including the first metal, and a second metal silicide capping layer contacting the first metal silicide capping layer and disposed on the lower conductive barrier film, the second metal silicide capping layer including the second metal.Type: GrantFiled: September 7, 2017Date of Patent: October 8, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-jine Park, Kee-sang Kwon, Jae-jik Baek, Yong-sun Ko, Kwang-wook Lee
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Patent number: 10373973Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.Type: GrantFiled: April 24, 2018Date of Patent: August 6, 2019Assignee: SK hynix Inc.Inventors: Won Joon Choi, Min Sung Ko, Kyeong Bae Kim, Jong Gi Kim, Dong Sun Sheen, Jung Myoung Shim, Young Ho Yang, Hyeng Woo Eom, Kwang Wook Lee, Woo Jae Chung
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Publication number: 20190096712Abstract: Disclosed are a supercritical process chamber and an apparatus having the same. The process chamber includes a body frame having a protrusion protruding in an upward vertical direction from a first surface of the body frame and a recess defined by the protrusion and the first surface of the body frame; a cover frame; a buffer chamber arranged between the body frame and the cover frame; and a connector. The buffer chamber includes an inner vessel detachably coupled to the body frame providing a chamber space in the recess and an inner cover detachably coupled to the cover frame. The inner cover is in contact with a first surface of the inner vessel enclosing the chamber space from surroundings. The connector couples the body frame and the cover frame having the buffer chamber arranged therebetween such that the enclosed chamber space is transformed into a process space in which the supercritical process is performed.Type: ApplicationFiled: May 14, 2018Publication date: March 28, 2019Inventors: Sang-Jine PARK, Byung-Kwon CHO, Yong-Jhin CHO, Yong-Sun KO, Yeon-Jin GIL, Kwang-Wook LEE
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Publication number: 20190081066Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.Type: ApplicationFiled: April 24, 2018Publication date: March 14, 2019Inventors: Won Joon CHOI, Min Sung KO, Kyeong Bae KIM, Jong Gi KIM, Dong Sun SHEEN, Jung Myoung SHIM, Young Ho YANG, Hyeng Woo EOM, Kwang Wook LEE, Woo Jae CHUNG
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Publication number: 20180293583Abstract: Provided is a method comprising acquiring information on a branch formed on blockchain data, calculating a difference in a block height between a target block corresponding to a current block height of the blockchain data and a block in a non-branched state based on the information on the branch and calculating a transaction confirmation reliability of transaction data recorded in the target block based on the difference in the block height, wherein the transaction confirmation reliability indicates a probability that, for as k blocks are further connected after the target block, a position of the block at which the transaction data is recorded will not change, wherein k is an integer greater than zero.Type: ApplicationFiled: March 23, 2018Publication date: October 11, 2018Applicant: SAMSUNG SDS CO., LTD.Inventors: Ji Hwan RHIE, Hee Jung WANG, Kwang Wook LEE, Dong Hoe KIM, Seung Won SON
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Publication number: 20180254246Abstract: An integrated circuit device includes an insulating film on a substrate, a lower wiring layer penetrating at least a portion of the insulating film, the lower wiring layer including a first metal, a lower conductive barrier film surrounding a bottom surface and a sidewall of the lower wiring layer, the lower conductive barrier film including a second metal different from the first metal, a first metal silicide capping layer covering a top surface of the lower wiring layer, the first metal silicide capping layer including the first metal, and a second metal silicide capping layer contacting the first metal silicide capping layer and disposed on the lower conductive barrier film, the second metal silicide capping layer including the second metal.Type: ApplicationFiled: September 7, 2017Publication date: September 6, 2018Inventors: Sang-jine PARK, Kee-sang KWON, Jae-jik BAEK, Yong-sun KO, Kwang-wook LEE
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Patent number: 9136135Abstract: A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, and etching sides of the gate pattern using a first wet-etching process to form a first recess. The first wet-etching process includes using an etchant containing a first chemical substance including a hydroxyl functional group (—OH) and a second chemical substance capable of oxidizing the substrate. The concentration of the second chemical substance is 1.5 times or less the concentration of the first chemical substance.Type: GrantFiled: July 17, 2013Date of Patent: September 15, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Jik Baek, Ji-Hoon Cha, Bo-Un Yoon, Kwang-Wook Lee, Jeong-Nam Han
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Patent number: 8748254Abstract: A method of manufacturing a semiconductor device includes forming a bit line on a substrate comprising an active region; forming an interlayer insulating layer covering the bit line on the substrate; forming a first hole at a location of the active region through the interlayer insulating layer; forming a dummy contact layer by filling the first hole; forming a mold layer on the interlayer insulating layer and the dummy contact layer; forming a second hole at a location of the dummy contact layer through the mold layer; removing the dummy contact layer in the first hole through the second hole; forming an epitaxial layer on a portion of the active region, which is exposed at a lower surface of the first hole; and forming a lower electrode on internal surfaces of the first hole and the second hole.Type: GrantFiled: June 12, 2012Date of Patent: June 10, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-wook Lee, Sang-jun Lee, In-seak Hwang, In-sang Jeon, Byoung-yong Gwak, Ho-kyun An
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Publication number: 20140080296Abstract: A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, and etching sides of the gate pattern using a first wet-etching process to form a first recess. The first wet-etching process includes using an etchant containing a first chemical substance including a hydroxyl functional group (—OH) and a second chemical substance capable of oxidizing the substrate. The concentration of the second chemical substance is 1.5 times or less the concentration of the first chemical substance.Type: ApplicationFiled: July 17, 2013Publication date: March 20, 2014Inventors: Jae-Jik BAEK, Ji-Hoon CHA, Bo-Un YOON, Kwang-Wook LEE, Jeong-Nam HAN
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Patent number: 8604550Abstract: A semiconductor device includes a semiconductor substrate having at least two oblique side surfaces and a first bottom surface in a recessed portion. A gate insulating layer is formed on the recessed portion. A gate electrode is formed on the gate insulating layer. A channel region is formed below the gate electrode. Gate spacers are formed on side surfaces of the gate electrode.Type: GrantFiled: April 29, 2011Date of Patent: December 10, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-Wook Lee, Jae-Jik Baek, In-Seak Hwang, Seok-Woo Nam
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Publication number: 20130052787Abstract: A method of manufacturing a semiconductor device includes forming a bit line on a substrate comprising an active region; forming an interlayer insulating layer covering the bit line on the substrate; forming a first hole at a location of the active region through the interlayer insulating layer; forming a dummy contact layer by filling the first hole; forming a mold layer on the interlayer insulating layer and the dummy contact layer; forming a second hole at a location of the dummy contact layer through the mold layer; removing the dummy contact layer in the first hole through the second hole; forming an epitaxial layer on a portion of the active region, which is exposed at a lower surface of the first hole; and forming a lower electrode on internal surfaces of the first hole and the second hole.Type: ApplicationFiled: June 12, 2012Publication date: February 28, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang-wook Lee, Sang-jun Lee, In-seak Hwang, In-sang Jeon, Byoung-yong Gwak, Ho-kyun An
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Patent number: 8086763Abstract: A class changing apparatus includes a link unit configured to be linked with a client device to transmit and receive data. The class change apparatus also includes a storage unit configured to store apparatus information including class information of the client device. The class changing apparatus further includes a control unit coupled to the link unit and the storage unit and controlling operations of the class changing apparatus including a class changing operation, wherein the class change operation includes transmitting at least one command including a command for rebranching into the selected class to the client device through the link unit and registering class information as changed class information in the storage unit in response to detecting a class change request.Type: GrantFiled: July 24, 2009Date of Patent: December 27, 2011Assignee: LG Electronics Inc.Inventors: Moo-Rak Choi, Kwang-Wook Lee, You-Sun Kim, Sung-Jea Ko
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Publication number: 20110284968Abstract: A semiconductor device includes a semiconductor substrate having a top surface and a recessed portion including at least two oblique side surfaces and a first bottom surface therebetween, a gate insulating layer formed on the recessed portion, a gate electrode formed on the gate insulating layer, a channel region below the gate electrode in the semiconductor substrate, and gate spacers formed on side surfaces of the gate electrode, wherein both the bottom surface and the side surfaces of the recessed portion include flat surfaces. A method of manufacturing a semiconductor device comprising the steps of forming a recess portion including at least two oblique side surfaces and a bottom surface therebetween in a semiconductor substrate, forming a gate insulating layer formed on the recessed portion, forming a gate electrode formed on the gate insulating layer, forming a channel region below the gate electrode in the semiconductor substrate, and forming gate spacers formed on side surfaces of the gate electrode.Type: ApplicationFiled: April 29, 2011Publication date: November 24, 2011Inventors: Kwang-Wook Lee, Jae-Jik Baek, In-Seak Hwang, Seok-Woo Nam
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Patent number: 7888725Abstract: An electronic device may include a substrate and a plurality of conductive electrodes on the substrate. Each of the conductive electrodes may have a respective electrode wall extending away from the substrate, and an electrode wall of at least one of the conductive electrodes may include a recessed portion. In addition, an insulating layer may be provided on the electrode wall, and portions of the electrode wall may be free of the insulating layer between the substrate and the insulating layer.Type: GrantFiled: October 3, 2008Date of Patent: February 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: In-joon Yeo, Tae-hyuk Ahn, Kwang-wook Lee, Jung-woo Seo, Jeong-sic Jeon
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Patent number: 7781346Abstract: A semiconductor structure may be formed by a wet etching process using an etchant containing water. The semiconductor structure may include a plurality of patterns having an increased or higher aspect ratio and may be arranged closer to one another. A dry cleaning process may be performed using hydrogen fluoride gas on the semiconductor structure.Type: GrantFiled: June 20, 2006Date of Patent: August 24, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Cheol-Woo Park, Byoung-Moon Yoon, Yong-Sun Ko, Kyung-Hyun Kim, Kwang-Wook Lee
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Publication number: 20100023649Abstract: A class changing apparatus includes a link unit configured to be linked with a client device to transmit and receive data. The class change apparatus also includes a storage unit configured to store apparatus information including class information of the client device. The class changing apparatus further includes a control unit coupled to the link unit and the storage unit and controlling operations of the class changing apparatus including a class changing operation, wherein the class change operation includes transmitting at least one command including a command for rebranching into the selected class to the client device through the link unit and registering class information as changed class information in the storage unit in response to detecting a class change request.Type: ApplicationFiled: July 24, 2009Publication date: January 28, 2010Applicant: LG ELECTRONICS INC.Inventors: Moo-Rak CHOI, Kwang-Wook LEE, You-Sun KIM, Sung-Jea KO
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Patent number: 7491601Abstract: An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer, and portions of the electrode most distant from the substrate may be free of the insulating spacer. Related methods and structures are also discussed.Type: GrantFiled: December 14, 2007Date of Patent: February 17, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: In-joon Yeo, Tae-hyuk Ahn, Kwang-wook Lee, Jung-woo Seo, Jeong-sic Jeon