Abstract: Disclosed are a substrate supporting unit, a substrate processing apparatus, and a method of manufacturing the substrate supporting unit. The substrate supporting unit includes a susceptor (12) provided with heaters (15a, 16b) to heat a substrate placed on the susceptor (12), and including a first temperature region and a second temperature region having a higher temperature than that of the first temperature region; and a heat dissipating member (20) including a contact surface (21) being in thermal contact with the second temperature region. The heat dissipating member (20) further includes an opening (23) corresponding to the first temperature region. The heat dissipating member (20) formed in a ring shape, in which the opening (23) is surrounded with the contact surface (21), and the contact surface (21) of the heat dissipating member (20) makes thermal contact with the lower surface of the susceptor (12).

Abstract: A plasma processing apparatus includes a chamber providing an interior space where a process is performed upon a target; and a plasma generating unit generating an electric field in the interior space to generate plasma from a source gas supplied to the interior space. The plasma generating unit includes an upper source disposed substantially parallel to an upper surface of the chamber, an upper generator connected to the upper source to supply a first current to the upper source, a lateral source surrounding a lateral side of the chamber, and a lateral generator connected to the lateral source to supply a second current to the lateral source. The plasma generating unit further includes an upper matcher disposed between the upper generator and the upper source, and a lower matcher disposed between the lateral generator and the lateral source.

Abstract: A plasma processing apparatus includes a chamber to provide an inner area in which a process is performed upon an object, and a plasma source to generate an electric field in the inner area and thereby to generate plasma from a source gas supplied in the inner area, wherein the plasma source comprises a top source provided in the top of the chamber, and a side source encompassing the side of the chamber and allowing current to flow from the one side of the chamber to the other side thereof.

Abstract: An image quality control system and method is disclosed. At least one infrared camera takes a screen image of a room. When there are a plurality of cameras, images of the cameras are synchronized with respect to time, and a specific object of the image is tracked to estimate image quality of the object. When there are a plurality of cameras, a 3D screen model is reconfigured, and positions of the cameras and the infrared lighting tools are controlled. Infrared lighting and the cameras are controlled, and particularly, optical axis direction, optical magnification, exposure time, and the iris of the camera can be amended. Next, a high-quality object image list can be generated so as to process the images.

Abstract: The present invention relates to an apparatus for controlling temperature of an optical module using an uncooled laser diode. A first setup unit for establishing low-temperature setup voltage and a second setup unit for establishing high-temperature setup voltage determine first and second threshold voltages suitable for low-temperature and high-temperature setup voltages, respectively. First and second comparators compare the low-temperature and high-temperature setup voltages with sensor voltage received from a sensor voltage entry unit, respectively. The output signals of the comparators are applied to a logic circuit, such that the logic circuit generates on/off signals according to the result of the comparison. The logic circuit generates a high-level signal only when the sensor voltage escaped from a predetermined voltage range, and thus operates the temperature control circuit.

Abstract: A database query system is provided. The database cache system includes: a network library which processes an access request issued by the online game server by using an input output completion port (IOCP); at least one database connection module which provides a connector for reading data from the database or recording data to the database; a database cache which stores data read from the database by the database connection module; and at least one cache buffer which is allotted to an IOCP worker thread corresponding to a database query request issued by the online game server and stores data read from the database, which is to be transmitted to the online game server.

Abstract: A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.

Abstract: A structure of a 2-bit mask ROM device and a fabrication method thereof are provided. The memory structure includes a substrate, a gate structure, a 2-bit coding implantation region, a spacer, a buried drain region, an isolation structure and a word line. The gate structure is disposed on the substrate, while the coding implantation region is located in the substrate under the side of the gate structure. Further, at least one spacer is arranged beside the side of the gate structure and a buried drain region is disposed in the substrate beside the side of the spacer. Moreover, the buried drain region and the coding implantation region further comprise a buffer region in between. Additionally, an insulation structure is arranged on the substrate that is above the buried drain region, while the word lien is disposed on the gate structure.

Abstract: An optical communication module is provided with a platform to provide an accurate axial alignment with optical transceiving subassemblies. In the optical communication module, axes of the optical transceiving sub-assemblies are aligned by virtue of previously established axial alignment of the platform, and the platform is fixed to a main body by inserting an insertion jaw of a cover into an insertion groove formed on an upper surface of the platform. After the optical transceiving subassemblies are inserted into the platform having the axial alignment required for a system, a bonding agent is filled into spaces defined in the platform, thereby preventing the axes from deviated by an external force.

Abstract: A latch type optical communication module, designed to9 be easily mounted and detached to a system port having a cage by means of a latch. The optical communication module is provided with a latch: The latch may be rotated around a hinge shaft fixed to both sides of a receptacle while being inserted into latch holes penetrating both ends of the latch. When the latch is rotated and then allows latch drivers to force a slider upward, the slider raises a fixing tap of the optical communication module inserted into the system port, thereby allowing the optical communication module to be detached from the system port. With the construction of the optical communication module, the plurality of additional components are not required for the optical communication module, thereby lowering manufacturing costs, and the optical communication module can be detached from the system port without any tool and any influence against adjacent optical communication module.

Abstract: A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.

Abstract: A method of manufacturing chalcogenide memory in a semiconductor substrate.

Abstract: A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.

Abstract: The application discloses a method of diagnosing an autoimmune disease in a mammal comprising: a) obtaining an antibody-containing sample from a subject suspected of suffering from the autoimmune disease, b) contacting said sample with a composition comprising PARP polypeptide; and c) detecting the presence of PARP polypeptide antigen/anti-PARP polypeptide antibody complex, which is indicative of the presence of the autoimmune disease.

Abstract: A fabrication method for a mask read only memory device is described. The method provides a substrate, and a doped conductive layer is formed on the substrate. After this, the doped conductive layer is patterned to form a plurality of bar-shaped doped conductive layers, followed by forming a dielectric layer on the substrate and on the bar-shaped conductive layers by thermal oxidation. A plurality of diffusion regions are concurrently formed under the bar-shaped conductive layers in the substrate. A patterned conductive layer is further formed on the dielectric layer.

Abstract: A mask ROM device is described. The mask ROM device includes a substrate, a gate, a double diffused source/drain region that comprises a first doped region and a second doped region, a channel region, a coding region, a dielectric layer and a word line. The gate is disposed on the substrate. The double diffused source/drain region is positioned beside the sides of the gate in the substrate, wherein the second doped region is located at the periphery of the first doped region in the substrate. The channel region is located between the double diffused source/drain region in the substrate. The coding region is disposed in the substrate at the intersection between the sides of the channel region and the double diffused source/drain region. The dielectric layer is disposed above the double diffused source/drain region, while the word line is disposed above the dielectric layer and the gate.

Abstract: A fabrication method for a flash memory device with a split floating gate is described. The method provides a substrate, wherein an oxide layer and a patterned sacrificial layer are sequentially formed on the substrate. Ion implantation is then conducted to form source/drain regions with lightly doped source/drain regions in the substrate beside the sides of the patterned sacrificial layer using the patterned sacrificial layer as a mask. Isotropic etching is further conducted to remove a part of the patterned sacrificial layer, followed by forming two conductive spacers on the sidewalls of the patterned sacrificial layer. The patterned sacrificial layer and oxide layer that is exposed by the two conductive spacers are then removed to form two floating gates. Subsequently, a dielectric layer and a control gate are formed on the substrate.

Abstract: A method for fabricating a non-volatile memory is described. A substrate having a strip stacked structure thereon is provided. A buried drain is then formed in the substrate beside the strip stacked structure and an insulating layer is formed on the buried drain. A silicon layer and a cap layer are sequentially formed over the substrate. The cap layer, the silicon layer and the strip stacked structure are then patterned successively in a direction perpendicular to the buried drain, wherein the strip stacked structure is patterned into a plurality of gates. A liner oxide layer is formed on the exposed surfaces of the gates, the substrate and the silicon layer. Thereafter, the cap layer is removed and a metal salicide layer is formed on the exposed surface of the silicon layer.

Abstract: A fabrication method for a mask read only memory device is described. The method provides a substrate, and a doped conductive layer is formed on the substrate. After this, the doped conductive layer is patterned to form a plurality of bar-shaped doped conductive layers, followed by forming a dielectric layer on the substrate and on the bar-shaped conductive layers by thermal oxidation. A plurality of diffusion regions are concurrently formed under the bar-shaped conductive layers in the substrate. A patterned conductive layer is further formed on the dielectric layer.

Abstract: A NROM cell for reducing for reducing the second-bit effect is described. The NORM cell of the present invention is formed with a substrate, a silicon oxide/silicon nitride/silicon oxide (ONO) layer disposed on the substrate, a gate disposed on the silicon oxide/silicon nitride/silicon oxide layer, source/drain regions configured in the substrate beside the gate, and a shallow pocket doped region configured between the source/drain regions and the ONO layer beside the gate. The depth of the shallow pocket doped region is sufficiently small to prevent interference to the current flow that travels to the source/drain regions.