Abstract: A substrate can include a feature pattern included in an integrated circuit on the substrate and an in-situ metrology pattern spaced apart from the feature pattern on the substrate, the in-situ metrology pattern and the feature pattern both configured to have equal heights relative to a surface of the substrate.

Abstract: A semiconductor device including a substrate including a first and second region; a first active region formed in an upper portion of the substrate in the first region; a second active region formed in an upper portion of the substrate in the second region; a first gate structure extending across the first active region, having a first gate length, and including a first high-k dielectric layer, a first lower metal layer, and a first upper metal layer; a second gate structure extending across the second active region, having a second gate length, and including a second high-k dielectric layer, a second lower metal layer having at least one metal layer, and a second upper metal layer; and spacers at sides of each of the first and second gate structures, a cross section of each of the first and second high-k dielectric layers has a U-shape, a cross section of each of the first and second lower metal layers has a U-shape, the first and second lower metal layers covering bottom surfaces and inner side surfaces of

Abstract: A photomask includes a focus metrology mark region that includes a plurality of focus monitor patterns. To measure a focal variation of a feature pattern formed on a substrate, a substrate target for lithography metrology including a focus metrology mark formed on the same level as the feature pattern is used. A lithography metrology apparatus includes a projection device including a polarizer; a detection device detecting the powers of ±n-order diffracted light beams from among output beams diffracted by the focus metrology mark of a to-be-measured substrate; and a determination device which determines, from a power deviation between the ±n-order diffracted light beams, defocus experienced by the feature pattern.

Abstract: In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.

Abstract: In a method of manufacturing a semiconductor device, an isolation layer pattern is formed on a substrate to define a field region covered by the isolation layer pattern and first and second active regions that is not covered by the isolation layer pattern and protrudes from the isolation layer pattern. A first anti-reflective layer is formed on the isolation layer pattern. A first photoresist layer is formed on the first and second active regions of the substrate and the first anti-reflective layer. The first photoresist layer is partially etched to form a first photoresist pattern covering the first active region. Impurities are implanted into the second active region to form a first impurity region.

Abstract: In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.

Abstract: A photomask includes a focus metrology mark region that includes a plurality of focus monitor patterns. To measure a focal variation of a feature pattern formed on a substrate, a substrate target for lithography metrology including a focus metrology mark formed on the same level as the feature pattern is used. A lithography metrology apparatus includes a projection device including a polarizer; a detection device detecting the powers of ±n-order diffracted light beams from among output beams diffracted by the focus metrology mark of a to-be-measured substrate; and a determination device which determines, from a power deviation between the ±n-order diffracted light beams, defocus experienced by the feature pattern.

Abstract: A substrate can include a feature pattern included in an integrated circuit on the substrate and an in-situ metrology pattern spaced apart from the feature pattern on the substrate, the in-situ metrology pattern and the feature pattern both configured to have equal heights relative to a surface of the substrate.

Abstract: Example embodiments relate to an overlay measurement device and method of forming an overlay pattern. The overlay measurement device includes a tray part with a substrate having a first region and a second region, a measurement part which measures an overlay of a first or second element, and a processor part which receives data measured by the measurement part and corrects the position of the first or second element, wherein the substrate comprises a first layer comprising the first overlay marks, a second layer comprising the second overlay marks, which intersects the first direction, in the second region and not comprising overlay marks which are used to measure the overlay of the second element; and the photoresist pattern which is formed on the first and second layers and overlaps the first and second overlay marks.

Abstract: A method of manufacturing a layer pattern of a semiconductor device, the method including forming an anti-reflective coating (ARC) layer on an etching object layer such that the ARC layer includes a polymer having an imide group; forming a photoresist pattern on the ARC layer; wet etching portions of the ARC layer exposed by the photoresist pattern to form an ARC layer pattern; and etching the etching object layer using the photoresist pattern as an etch mask to form the layer pattern.

Abstract: In a method of manufacturing a semiconductor device, an isolation layer pattern is formed on a substrate to define a field region covered by the isolation layer pattern and first and second active regions that is not covered by the isolation layer pattern and protrudes from the isolation layer pattern. A first anti-reflective layer is formed on the isolation layer pattern. A first photoresist layer is formed on the first and second active regions of the substrate and the first anti-reflective layer. The first photoresist layer is partially etched to form a first photoresist pattern covering the first active region. Impurities are implanted into the second active region to form a first impurity region.

Abstract: In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.

Abstract: A method of manufacturing a layer pattern of a semiconductor device, the method including forming an anti-reflective coating (ARC) layer on an etching object layer such that the ARC layer includes a polymer having an imide group; forming a photoresist pattern on the ARC layer; wet etching portions of the ARC layer exposed by the photoresist pattern to form an ARC layer pattern; and etching the etching object layer using the photoresist pattern as an etch mask to form the layer pattern.

Abstract: A method of forming fine patterns of a semiconductor device by using carbon (C)-containing films includes forming an etching target film on a substrate including first and second regions; forming a plurality of first C-containing film patterns on the etching target film in the first region; forming a buffer layer which covers top and side surfaces of the plurality of first C-containing film patterns; forming a second C-containing film; removing the second C-containing film in the second region; exposing the plurality of first C-containing film patterns by removing a portion of the buffer layer in the first and second regions; and etching the etching target film by using the plurality of first C-containing film patterns, and portions of the second C-containing film which remain in the first region, as an etching mask.

Abstract: A thinner composition includes propylene glycol ether acetate, methyl 2-hydroxy-2-methyl propionate, and an ester compound such as ethyl lactate, ethyl 3-ethoxy propionate or a mixture thereof.

Abstract: A method of forming fine patterns of a semiconductor device by using carbon (C)-containing films includes forming an etching target film on a substrate including first and second regions; forming a plurality of first C-containing film patterns on the etching target film in the first region; forming a buffer layer which covers top and side surfaces of the plurality of first C-containing film patterns; forming a second C-containing film; removing the second C-containing film in the second region; exposing the plurality of first C-containing film patterns by removing a portion of the buffer layer in the first and second regions; and etching the etching target film by using the plurality of first C-containing film patterns, and portions of the second C-containing film which remain in the first region, as an etching mask.

Abstract: In an optical member holder and a projection exposure apparatus having the same, a light beam radiated from a light source may be formed into light having a desired shape by selecting one of a plurality of optical elements. An optical element holder may include a support member to support the plurality of optical elements, a first driving section to move or rotate the support member to select one of the optical elements, and a second driving section to rotate the selected optical element to adjust an arrangement direction thereof. The light formed by the selected optical element may be directed through a reticle.

Abstract: In a method of manufacturing a capacitor and a method of manufacturing a dynamic random access memory device, an insulating layer covering an upper portion of a conductive layer may be provided with an ozone gas so as to change the property of the upper portion of the insulating layer. The upper portion of the insulating layer may be chemically removed to expose the upper portion of the conductive layer. The exposed upper portion of the conductive layer may be removed so as to transform the conductive layer into a lower electrode. The remaining portion of the insulating layer may be removed, and an upper electrode may be formed on the lower electrode.

Abstract: A thinner composition includes propylene glycol ether acetate, methyl 2-hydroxy-2-methyl propionate, and an ester compound such as ethyl lactate, ethyl 3-ethoxy propionate or a mixture thereof.

Abstract: A thinner composition includes propylene glycol ether acetate, methyl 2-hydroxy-2-methyl propionate, and an ester compound such as ethyl lactate, ethyl 3-ethoxy propionate or a mixture thereof.