Abstract: A semiconductor device comprises a first wiring that receives an input signal and extends in a first direction, a first gate wiring that extends in a second direction that intersects the first direction, a first impurity region disposed on one side of the first gate wiring and is connected to the first wiring, a second impurity region disposed on an other side of the first gate wiring and is connected to the first wiring, a second gate wiring that extends in the second direction and is spaced apart from the first gate wiring in the first direction and is connected to the first wiring, and a first inverter that includes the second gate wiring and is connected to the first wiring through which the inverter receives the input signal.

Abstract: A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.

Abstract: To design an integrated circuit, input data defining an integrated circuit are received, and a plurality of load standard cells having different delay characteristics are provided in a standard cell library. Placement and routing are performed based on the input data and the standard cell library and output data defining the integrated circuit are generated based on a result of the placement and the routing. Design efficiency and performance of the integrated circuit are enhanced by designing the integrated circuit with delay matching and duty ratio adjustment using the load standard cell.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.

Abstract: A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.

Abstract: To design an integrated circuit, input data defining an integrated circuit are received, and a plurality of load standard cells having different delay characteristics are provided in a standard cell library. Placement and routing are performed based on the input data and the standard cell library and output data defining the integrated circuit are generated based on a result of the placement and the routing. Design efficiency and performance of the integrated circuit are enhanced by designing the integrated circuit with delay matching and duty ratio adjustment using the load standard cell.

Abstract: A delay control circuit includes: a first step delay cell including a first switch having a first end connected to a first node, and a first capacitor connected to a second end of the first switch; a second step delay cell including a second switch having a first end connected to a second node, and a second capacitor connected to a second end of the second switch; and a first inverter configured to couple an output signal of the first step delay cell to an input of the second step delay cell, wherein the first switch and the second switch are turned on and off by a same control signal.

Abstract: A delay-locked loop (DLL) circuit and an integrated circuit (IC) including the same are provided. The DLL circuit includes a pre-processing circuit configured to generate a first pulse signal and a second pulse signal based on a clock signal input, the first pulse signal and the second pulse signal having a phase difference of (s/2) times a clock period of the clock signal (where s is a positive integer), a delay line configured to generate a delay signal by delaying the first pulse signal by a delay amount corresponding to a selection value, a phase detector configured to detect a phase difference between the delay signal and the second pulse signal, and a control logic configured to adjust the selection value based on the phase difference between the delay signal and the second pulse signal as detected by the phase detector, so as to synchronize the delay signal with the second pulse signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A delay-locked loop (DLL) circuit and an integrated circuit (IC) including the same are provided. The DLL circuit includes a pre-processing circuit configured to generate a first pulse signal and a second pulse signal based on a clock signal input, the first pulse signal and the second pulse signal having a phase difference of (s/2) times a clock period of the clock signal (where s is a positive integer), a delay line configured to generate a delay signal by delaying the first pulse signal by a delay amount corresponding to a selection value, a phase detector configured to detect a phase difference between the delay signal and the second pulse signal, and a control logic configured to adjust the selection value based on the phase difference between the delay signal and the second pulse signal as detected by the phase detector, so as to synchronize the delay signal with the second pulse signal.

Abstract: A data processing circuit includes a delay circuit configured to delay a data signal and generate delayed data signals each having a different delay; and an output control circuit configured to output a first data signal among the delayed data signals as a data signal sampled at a first edge of a sampling clock signal, and output a second data signal among the delayed data signals as a data signal sampled at a second edge of the sampling clock signal.

Abstract: A delay cell includes first through fifth inversion circuits. The first inversion circuit inverts an input signal, and an output electrode of the first inversion circuit is coupled to a first node. The second inversion circuit is turned on in response to a control signal, and inverts the input signal when turned on. An output electrode of the second inversion circuit is coupled to the first node. The third inversion circuit inverts a signal at the first node, and an output electrode of the third inversion circuit is coupled to a second node. The fourth inversion circuit is turned on in response to the control signal, and inverts the signal at the first node when turned on. An output electrode of the fourth inversion circuit is coupled to the second node. The fifth inversion circuit inverts a signal at the second node to generate an output signal.

Abstract: A delay cell includes first through fifth inversion circuits. The first inversion circuit inverts an input signal, and an output electrode of the first inversion circuit is coupled to a first node. The second inversion circuit is turned on in response to a control signal, and inverts the input signal when turned on. An output electrode of the second inversion circuit is coupled to the first node. The third inversion circuit inverts a signal at the first node, and an output electrode of the third inversion circuit is coupled to a second node. The fourth inversion circuit is turned on in response to the control signal, and inverts the signal at the first node when turned on. An output electrode of the fourth inversion circuit is coupled to the second node. The fifth inversion circuit inverts a signal at the second node to generate an output signal.