Abstract: A semiconductor memory device includes: an input control circuit suitable for providing an active address which is input together with an active command, as an input address; a plurality of latches suitable for sequentially storing, as a latch address, the input address according to input control signals and outputting the latch addresses as a target address according to output control signals; a plurality of counters respectively corresponding to the latches and each suitable for increasing, when the active address matches the latch address stored in the latch, a counting value corresponding to the latch; and a refresh controller suitable for dividing the counters and the latches into a plurality of groups based on the counting values and generating, in response to a refresh command, reset signals for initializing the counters included in one group of the groups.

Abstract: A semiconductor memory device includes: an input control circuit suitable for providing an active address which is input together with an active command, as an input address; a plurality of latches suitable for sequentially storing, as a latch address, the input address according to input control signals and outputting the latch addresses as a target address according to output control signals; a plurality of counters respectively corresponding to the latches and each suitable for increasing, when the active address matches the latch address stored in the latch, a counting value corresponding to the latch; and a refresh controller suitable for dividing the counters and the latches into a plurality of groups based on the counting values and generating, in response to a refresh command, reset signals for initializing the counters included in one group of the groups.

Abstract: A semiconductor memory device comprises: first storage logic configured to store, as first addresses, ‘K’ addresses having different values among input addresses applied during the enable period of a reference signal, second storage logic configured to store, as second addresses, ‘L’ addresses corresponding to a time point at which the enable period of the reference signal is ended among the input addresses, an order controller configured to determine a first output order of each of the first addresses based on a number of times each of the first addresses is repeatedly input, and to determine a second output order for outputting mixed addresses obtained by mixing the first addresses based on the first output order and the second addresses together, and refresh operation logic configured to apply the mixed addresses according to the second output order, to a target refresh operation.

Abstract: A nonvolatile memory apparatus and an operating method of the nonvolatile memory apparatus may include a first memory cell array, a second memory cell array, a bit line switch, and a sensing control signal generation circuit. The first and second memory cell arrays may be coupled to a bit line. The bit line switch may electrically couple the first memory cell array to the second memory cell array according to an operation period of the non-volatile memory apparatus.

Abstract: A nonvolatile memory apparatus and an operating method of the nonvolatile memory apparatus may include a first memory cell array, a second memory cell array, a bit line switch, and a sensing control signal generation circuit. The first and second memory cell arrays may be coupled to a bit line. The bit line switch may electrically couple the first memory cell array to the second memory cell array according to an operation period of the non-volatile memory apparatus.

Abstract: A semiconductor integrated circuit device may include a plurality of semiconductor chips, a scribe lane, connecting wiring, and a selection circuit. Each of the semiconductor chips may include a peripheral circuit. The scribe lane may be positioned between the semiconductor chips. A test pad may be arranged in the scribe lane. The connecting wiring may be connected between the test pad and the peripheral circuit. The selection circuit may be configured to selectively connect or disconnect the connecting wiring.

Abstract: A semiconductor integrated circuit device may include a plurality of semiconductor chips, a scribe lane, connecting wiring, and a selection circuit. Each of the semiconductor chips may include a peripheral circuit. The scribe lane may be positioned between the semiconductor chips. A test pad may be arranged in the scribe lane. The connecting wiring may be connected between the test pad and the peripheral circuit. The selection circuit may be configured to selectively connect or disconnect the connecting wiring.

Abstract: A rupture control device may include an address control circuit configured to generate a rupture address in response to a first rupture command signal, a rupture mask signal and an external address, wherein the rupture address is generated according to whether the rupture mask signal is activated, and wherein an address and fuse data are compared, and a rupture mask signal indicating whether a fuse is ruptured is determined. Further, a fuse array configured to perform a rupture operation in response to the rupture address when a rupture enable signal is activated, and output the fuse data in response to a read enable signal.

Abstract: A rupture control device may include an address control circuit configured to generate a rupture address in response to a first rupture command signal, a rupture mask signal and an external address, wherein the rupture address is generated according to whether the rupture mask signal is activated, and wherein an address and fuse data are compared, and a rupture mask signal indicating whether a fuse is ruptured is determined. Further, a fuse array configured to perform a rupture operation in response to the rupture address when a rupture enable signal is activated, and output the fuse data in response to a read enable signal.

Abstract: A memory device includes a non-volatile memory circuit suitable for storing system hard repair data, a temporary memory circuit suitable for storing system soft repair data, a system register circuit suitable for receiving and storing the system hard repair data or the system soft repair data during a boot-up operation, and a memory bank suitable for performing a repair operation based on first data stored in the system register circuit.

Abstract: A semiconductor memory device which performs a refresh operation. The semiconductor memory device may include an information detection unit suitable for detecting a refresh characteristic of a memory cell, a control signal generation unit suitable for generating a refresh control signal having a refresh cycle corresponding to the refresh characteristic, and a refresh driving unit suitable for driving a refresh operation on the memory cell with the refresh cycle in response to the refresh control signal.

Abstract: A semiconductor apparatus includes a plurality of unit memory blocks and a plurality of sense amplifier arrays configured to be shared with two or more unit memory blocks among the plurality of unit memory blocks, and amplify data of the unit memory blocks. When a unit memory block corresponding to an external address and a unit memory block corresponding to a refresh address among the plurality of unit memory blocks are coupled in common to one of the plurality of sense simplifier arrays, the semiconductor apparatus stores the refresh address and executes a normal operation command corresponding to the external address.

Abstract: A memory device may include a plurality of word lines each word line being operably coupled to one or more memory cells; a peripheral circuit suitable for performing first and second refresh operations to the plurality of word lines; wherein the first refresh operation is suitable for preserving stored data for a majority of the memory cells of the memory device and the second refresh operation is suitable for preserving stored data of one or more weak memory cells.

Abstract: Disclosed herein is a semiconductor memory device which performs a refresh operation. The semiconductor memory device may include an information detection unit suitable for detecting a refresh characteristic of a memory cell, a control signal generation unit suitable for generating a refresh control signal having a refresh cycle corresponding to the refresh characteristic, and a refresh driving unit suitable for driving a refresh operation on the memory cell with the refresh cycle in response to the refresh control signal.

Abstract: A semiconductor device includes a fuse array including verification fuses and normal fuses, a determination block suitable for reading data programmed in the verification fuses based on a read reference voltage and during a boot-up preparation section, determining whether or not a read value is the same as a predetermined value, and a level control block suitable for adjusting a level of the read reference voltage based on a determined result during the boot-up preparation section.

Abstract: A semiconductor memory device includes a plurality of redundancy cells suitable for repairing a defective cell of a plurality of normal cells, a defective redundancy cell information storing circuit block suitable for detecting whether the redundancy cells are defective and storing information on a redundancy cell that is detected to be defective, and a defective redundancy cell rupture circuit block suitable for performing a disable rupture operation on the redundancy cell that is detected to be defective.

Abstract: A memory device includes a non-volatile memory circuit suitable for storing system hard repair data, a temporary memory circuit suitable for storing system soft repair data, a system register circuit suitable for receiving and storing the system hard repair data or the system soft repair data during a boot-up operation, and a memory bank suitable for performing a repair operation based on first data stored in the system register circuit.

Abstract: A semiconductor device includes a fuse array including verification fuses and normal fuses, a determination block suitable for reading data programmed in the verification fuses based on a read reference voltage and during a boot-up preparation section, determining whether or not a read value is the same as a predetermined value, and a level control block suitable for adjusting a level of the read reference voltage based on a determined result during the boot-up preparation section.

Abstract: A DC-DC boost converter for a power generation element includes a power generation element configured to generate a both end voltage and a power supply current, an inductor charged by the power supply current, a first and second switch units comprising a plurality of first and second transistors, an MPPT control unit configured to detect the both end voltage and output a control signal to the first and second switch units so that an input voltage output from the power generation element is maintained as a predetermined proportion of the both end voltage, a current detection unit configured to output a signal for controlling the number of enabled first transistors and second transistors according to an intensity of the power supply current, and a switch selection unit configured to connect the first transistors and the second transistors through the signal.

Abstract: A semiconductor device includes a fuse unit connected to a detection node and configured to be programmed in response to a first voltage supplied through the detection node, an output unit connected to the detection node and configured to output a fuse information signal indicating whether the fuse unit is programmed or not, and a blocking unit configured to block the first voltage supplied through the detection node in response to the fuse information signal.