Abstract: An LC voltage-controlled oscillator (VCO) is provided. The LC VCO includes an LC resonant circuit including at least one inductor whose both terminals are connected to output nodes and at least one capacitor connected in parallel with the inductor, and an amplifier circuit including at least one pair of switching transistors. Here, drains of the pair of switching transistors are connected to the output nodes respectively, and gates of the switching transistors are connected with the drains through a variable capacitance block exhibiting different characteristics according to an input signal.

Abstract: A multi-bit test control circuit includes an operation unit, a delay unit, and a generation unit. The operation unit is configured to combine a single source signal inputted to each bank with a delay signal generated by delaying the source signal by a certain time to generate a first pulse signal. The delay unit is configured to delay the first pulse signal by a certain time. The generation unit is configured to combine an output signal of the operation unit with an output signal of the delay unit to generate a second pulse signal for a bank interleaving multi-bit test.

Abstract: Provided is a low voltage frequency synthesizer using a boosting method for a power supply voltage of a charge pump. The low voltage frequency synthesizer includes a phase/frequency detector (PFD) that receives and compares a reference frequency and a feedback frequency to output a comparison signal, a charge pump that receives the comparison signal to output a current corresponding to the comparison signal, a low-pass filter (LPF) that generates a voltage corresponding to the output current of the charge pump, a voltage controlled oscillator (VCO) that receives the voltage of the LPF, amplifies the voltage to generate a boosting voltage, and outputs a frequency corresponding to the received voltage, and a DC converter that receives the boosting voltage of the VCO, converts the boosting voltage into a DC voltage, and applies the DC voltage as a power supply voltage of the charge pump.

Abstract: A semiconductor memory device can determine whether control for supplying termination resistances is normally performed or not by applying a test signal. The device includes a termination resistance driving controller configured to receive a plurality of termination resistance setting signals in synchronization with an external clock and a delay locked loop (DLL) clock to output a plurality of pre-driving signals and a plurality of termination resistance driving signals for a predetermined time. A data pre-driver is configured to output data in synchronization with the external clock. A test driving detector is configured to drive output nodes to a predetermined voltage level in response to a test signal and the plurality of pre-driving signals. A data output buffer is configured to apply termination resistances corresponding to the plurality of termination resistance driving signals to input/output pads, and output the data from the output nodes to the input/output pads.

Abstract: An LC voltage-controlled oscillator (VCO) is provided. According to the LC voltage-controlled oscillator (VCO), the amplitude of an oscillation signal is improved by increasing the impedance value of an amplifier circuit seen from an output node in an LC voltage-controlled oscillator (VCO), and phase noise is also improved.

Abstract: Provided is a transformer-based oscillator which is suited to oscillate frequencies in multiple bands. An oscillator includes a transformer resonance unit and a plurality of complementary transistors. The transformer resonance unit includes a primary coil and a secondary coil corresponding to the primary coil. The plurality of complementary transistors have gates and drains between which both ends of the transformer resonance unit are respectively connected. Thus, the oscillator may operate in a differential mode or common mode according to the phase of the transformer resonance unit. Also, a complementary transistor constituting a multiband oscillation loop may be independently connected to both ends of the transformer resonance unit, and an oscillation loop of at least one band may be selected out of a multiband oscillation loop using a switch unit. Thus, the oscillator may be suited to oscillate resonance frequencies in multiple bands.

Abstract: A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks through a common data line in response to access information of the first and second memory banks.

Abstract: A semiconductor memory device includes a first memory bank and a second memory bank and a common write driver configured to drive write data to an activated memory bank of the first memory bank and the second memory bank. The common write driver of the semiconductor memory device includes a common write control block configured to generate common drive control signals corresponding to write data, and a common write drive block configured to drive transmission lines of a first memory bank or transmission lines of a second memory bank that are selected by a bank selection signal in response to the common drive control signals.

Abstract: Provided is a low voltage frequency synthesizer using a boosting method for a power supply voltage of a charge pump. The low voltage frequency synthesizer includes a phase/frequency detector (PFD) that receives and compares a reference frequency and a feedback frequency to output a comparison signal, a charge pump that receives the comparison signal to output a current corresponding to the comparison signal, a low-pass filter (LPF) that generates a voltage corresponding to the output current of the charge pump, a voltage controlled oscillator (VCO) that receives the voltage of the LPF, amplifies the voltage to generate a boosting voltage, and outputs a frequency corresponding to the received voltage, and a DC converter that receives the boosting voltage of the VCO, converts the boosting voltage into a DC voltage, and applies the DC voltage as a power supply voltage of the charge pump.

Abstract: Provided is a ring oscillator having an extended range of oscillation frequency by varactors coupled to delay cells even in a simple structure. The wide frequency range results from simply varying an oscillation frequency by control signals applied to the varactors. Since additional switches connected to the delay cells contribute to increase or decrease of the oscillation frequency range, the ring oscillator can conveniently be employed in various types of oscillation systems.

Abstract: Provided are a switching circuit and a small-size high-efficiency direct current-to-direct current (DC-DC) converter for portable devices including the same. Using dynamic threshold-complementary metal oxide semiconductor (DT-CMOS) transistors having dynamic threshold voltages as a switching device, the switching circuit maintains a low threshold voltage in a normal mode to improve current drivability while reducing conduction loss, and maintains a high threshold voltage in a standby mode to minimize power consumption. When the switching circuit is employed in a DC-DC converter, power conversion efficiency can be improved by reducing conduction loss in the normal mode, and power consumption can be minimized in the standby mode. Consequently, the DC-DC converter can maximize a use time of a battery of a portable device and can be useful in power supplies of portable devices that are gradually being miniaturized.

Abstract: A sensing enable signal control circuit determines a driving timing of an I/O sense amplifier based on a read-out result of data, which is stored in a dummy cell of a semiconductor memory apparatus. The sensing enable signal control circuit in a semiconductor memory apparatus includes a detection code generating unit configured to output a detection code according to a voltage level of dummy cell data, which are read out from a dummy cell through at least one read operation, in response to a column select enable signal, and a multiplexer configured to receive the detection code and a default code and output a delay code to delay a sensing enable signal.

Abstract: Provided is a gain amplifier having a switched-capacitor structure capable of minimizing settling time, in which an input capacitor is connected to an input terminal during a first clock sampling an input signal, and thus an output terminal of the amplifier is reset in advance to an estimated output voltage value rather than 0 by the input capacitor. Accordingly, the slight move of the output terminal of the amplifier is sufficient to settle to a desired value in an amplification mode, so that slewing time can be reduced, and as a result, overall settling time and power consumption can be minimized.

Abstract: Provided are a lock detection circuit and a lock detecting method. The lock detection circuit includes two delay devices, four flip-flops and two logic gates, and can accurately detect a lock state of a phase locked loop (PLL) circuit. Therefore, the lock detection circuit can be implemented in a simple structure, and as a result, the lock detection circuit can be compact in size and can consume less electric power. Also, the lock detecting method enables lock detection process to be simpler, so that a lock state can be detected within a short time period.

Abstract: Provided is a high-speed asynchronous digital signal level conversion circuit converting an input signal of a first voltage level into a signal of a second voltage level. The conversion circuit is able to operate at high speed by connecting first and second nodes, at which the input signal of the first voltage level is converted to the signal of the second voltage level, to a second power source voltage of the second voltage level for fast voltage level conversion when the voltage level of the input signal is changed.

Abstract: A control circuit for a read operation of a SERDES (SERializer and DESeriallizer) type semiconductor memory apparatus is disclosed that includes a first delay unit that is configured to generate and output a first delay signal to a first global input/output line driver by receiving a sensing-enable signal ‘IOSTB’, and to generate and output a second delay signal to a second global input/output line driver by receiving the sensing-enable signal. The first delay unit generates the second delay signal by delaying the sensing-enable signal in synchronization with a clock. The semiconductor memory apparatus also includes a second delay unit configured to generate a pipe latch control signal in response to the first delay signal and the second delay signal.

Abstract: The present invention relates to a circuit and a method for controlling a self-refresh cycle of a dynamic random access memory or DRAM. A cell voltage is directly detected so that a self-refresh cycle can be variably controlled. Detectors each detecting whether or not a voltage charged into a capacitor of a detection cell drops to or below a reference voltage and outputs a detection signal. A pulse generator generates a self-refresh pulse while being linked with an enabled detection signal of the plurality of detectors. A self-refresh cycle can be variably controlled and set to be suitable for the charging capacity of a cell. The detection cell is adapted to the change of the charging capacity of the cell in accordance with a change in temperature.

Abstract: The present invention relates to a circuit and a method for controlling a self-refresh cycle of a dynamic random access memory or DRAM. A cell voltage is directly detected so that a self-refresh cycle can be variably controlled. Detectors each detecting whether or not a voltage charged into a capacitor of a detection cell drops to or below a reference voltage and outputs a detection signal. A pulse generator generates a self-refresh pulse while being linked with an enabled detection signal of the plurality of detectors. A self-refresh cycle can be variably controlled and set to be suitable for the charging capacity of a cell. The detection cell is adapted to the change of the charging capacity of the cell in accordance with a change in temperature.

Abstract: Provided are a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling the same. The method includes the steps of: simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal and respectively generating a first sampling value and a second sampling value; holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code; and generating, at the residual signal generator, a residual signal using the digital code. The pipeline ADC and method of controlling the same minimize sampling mismatch caused by removing a front-end SHA, thereby ensuring stable performance without a front-end SHA. Since a front-end SHA is not used, it is possible to reduce chip size and power consumption, and improve the performance of the ADC.

Abstract: Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.