Abstract: An image processing apparatus. A rendering unit of the image processing apparatus may perform rendering with respect to each of N passes by applying a multi-pass rendering process with respect to an object in an image. The image processing apparatus may include a texture buffer to store information about at least one pixel using second pass rendering different from first pass rendering, while performing the first pass rendering corresponding to a process of generating a final result image among the N passes.

Abstract: An apparatus and method for converting a protocol interface are provided. A protocol converter may analyze a protocol of protocol data, and may sequentially output a plurality of sub-data of the input protocol data according to types of the plurality of sub-data and a plurality of phase information representing the types of the plurality of sub-data. A phase channel line may transmit phase information received from the protocol converter among the plurality of phase information. A data channel line may simultaneously transmit the received phase information and a sub-data corresponding to the received phase information.

Abstract: A processor for processing stream data at a high speed is provided. The processor may include a functional unit to perform an operation on the stream data, an input interface module to perform relaying between the functional unit and an external data producer module that is used to input the stream data to the processor, and an output interface module to perform relaying between the functional unit and an external data consumer module that is used to receive an input of result data regarding a result of the operation performed by the functional unit.

Abstract: An external intrinsic interface. A processor may include a core including a plurality of functional units, an intrinsic module located outside the core, and an interface module to perform relaying between the intrinsic module and a functional unit, among the plurality of functional units.

Abstract: Provided are a method and apparatus for avoiding bank conflict. A first instruction that is one of access instructions that are predicted to cause the bank conflict is replaced with a second instruction by changing an execute timing of the first instruction to a timing prior to the execute timing of the first instruction so as for the access instructions not to cause the bank conflict. Next, a load/store unit that is scheduled to access the bank according to the first instruction accesses the bank and reads out a data from the bank at an execute timing of the second instruction, and after that, the load/store unit is allowed to be inputted the read data at the execute timing of the first instruction. Accordingly, although the access instructions that are predicted to cause the bank conflict are allocated to the load/store units, the bank conflict can be prevented, so that it is possible to avoid deterioration in performance due the occurrence of the bank conflict.

Abstract: A bus arbitration apparatus and method are provided. A plurality of masters may be classified into master types based on master characteristics, and bus arbitration may be performed. Thus, it is possible to prevent a bus from being distributed to a predetermined master, and it is possible to improve overall performance of a bus system by solving a problem of unbalanced distribution of performance between the plurality of masters.

Abstract: A processor and an operating method are described. By diversifying an L1 memory being accessed, based on an execution mode of the processor, an operating performance of the processor may be enhanced. By disposing a local/stack section in a system dynamic random access memory (DRAM) located external to the processor, a size of a scratch pad memory may be reduced without deteriorating a performance. While a core of the processor is performing in a very long instruction word (VLIW) mode, the core may data-access a cache memory and thus, a bottleneck may not occur with respect to the scratch pad memory even though a memory access occurs with respect to the scratch pad memory by an external component.

Abstract: Provided is a method and apparatus for rendering 3D graphics data. By calculating the size of a primitive, which is a basic constituent unit of objects indicated by the graphics data, on a screen, selecting one of a plurality of resolutions supported by a video stream according to the calculated size, generating a video frame image having the selected resolution from the video stream, and rendering the graphics data using the generated video frame image, the amount of memory space used and power consumed are reduced. In addition, since when rendering is performed using a video frame image decoded at a low resolution, a processing speed increases, and since rendering can be performed using video frame images decoded at various resolutions, image quality increases.

Abstract: A processor and a memory controlling method. The processor enables a Scratch-Pad Memory (SPM) to prepare data that a processor core intends to process, using a data management unit including a data cache, thereby increasing a data processing rate.

Abstract: An apparatus and method for converting a protocol interface are provided. A protocol converter may analyze a protocol of protocol data, and may sequentially output a plurality of sub-data of the input protocol data according to types of the plurality of sub-data and a plurality of phase information representing the types of the plurality of sub-data. A phase channel line may transmit phase information received from the protocol converter among the plurality of phase information. A data channel line may simultaneously transmit the received phase information and a sub-data corresponding to the received phase information.

Abstract: Disclosed are a reconfigurable processor and processing method, a reconfiguration control apparatus and method, and a thread modeler and modeling method. A memory area of a reconfigurable processor may be divided into a plurality of areas, and a context enabling a thread process may be stored in respective divided areas, in advance. Accordingly, when a context switching is performed from one thread to another thread, the other thread may be executed by using information stored in an area corresponding to the other thread.

Abstract: A tile based rendering apparatus and method is provided. The rendering method may be used to graphically represent a three dimensional (3D) model on a two dimensional (2D) display screen. Also, the rendering method may perform pre-binning with respect to objects included in a frame, and thus all geometry processing results may not be stored in an external memory and use of the external memory may be reduced.

Abstract: A processor and a memory controlling method. The processor enables a Scratch-Pad Memory (SPM) to prepare data that a processor core intends to process, using a data management unit including a data cache, thereby increasing a data processing rate.

Abstract: An apparatus and method of reading texture data for texture mapping. Each of a plurality of blocks included in a cache memory may have any one of an even numbered index or odd numbered index. In this instance, the cache memory may be embodied with an odd numbered index cache memory including odd numbered index blocks and an even numbered index cache memory including even numbered index blocks. Also, address indexes of requested texture data may be analyzed to appropriately access to at least one of the odd numbered index cache memory and even numbered index cache memory, thereby improving an accessing speed.

Abstract: A method and apparatus of processing three-dimensional (3D) graphic data using a texture factor. The method of processing 3D graphic data includes configuring a polygon including a plurality of vertexes, calculating a texture factor of an object texture corresponding to the polygon, the texture factor being associated with a degree by which the object texture is identified on an actual screen, and determining a texture filtering mode with respect to the object texture based on the calculated texture factor.

Abstract: A rendering apparatus and method are provided. The rendering method includes: reading a block, corresponding to a fragment, from among compressed blocks stored in a depth buffer, by considering frequency information corresponding to the fragment and prepared in advance; and performing a depth test for the fragment by considering the restored block.

Abstract: A rendering method and apparatus are provided. The rendering method includes: performing texture mapping of a transparency value of a fragment; testing whether or not the fragment can be expressed as a pixel after the performing of the texture mapping; and selectively performing texture mapping of the color value of the fragment according to the test result.

Abstract: Provided are a method and apparatus for avoiding bank conflict. A first instruction that is one of access instructions that are predicted to cause the bank conflict is replaced with a second instruction by changing an execute timing of the first instruction to a timing prior to the execute timing of the first instruction so as for the access instructions not to cause the bank conflict. Next, a load/store unit that is scheduled to access the bank according to the first instruction accesses the bank and reads out a data from the bank at an execute timing of the second instruction, and after that, the load/store unit is allowed to be inputted the read data at the execute timing of the first instruction. Accordingly, although the access instructions that are predicted to cause the bank conflict are allocated to the load/store units, the bank conflict can be prevented, so that it is possible to avoid deterioration in performance due the occurrence of the bank conflict.

Abstract: Provided is a method and apparatus for rendering 3D graphics data. By calculating the size of a primitive, which is a basic constituent unit of objects indicated by the graphics data, on a screen, selecting one of a plurality of resolutions supported by a video stream according to the calculated size, generating a video frame image having the selected resolution from the video stream, and rendering the graphics data using the generated video frame image, the amount of memory space used and power consumed are reduced. In addition, since when rendering is performed using a video frame image decoded at a low resolution, a processing speed increases, and since rendering can be performed using video frame images decoded at various resolutions, image quality increases.