Patents by Inventor Ky-Hyun Han

Ky-Hyun Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7589006
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of gate lines on a substrate, forming a first cell spacer on the gate lines, forming a second cell spacer on the first cell spacer, forming a buffer layer on the second cell spacer, and exposing the surface of the substrate by etching the buffer layer.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: September 15, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki-Won Nam, Ky-Hyun Han
  • Patent number: 7585723
    Abstract: A method for fabricating a semiconductor device includes forming an insulation structure over a substrate structure including contact plugs, etching the insulation structure to form opening regions each of which has a lower opening portion having a critical dimension wider than an upper opening portion, and forming a conductive layer contacting the contact plugs inside the opening regions.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: September 8, 2009
    Assignee: Hynix Semiconductor Inc
    Inventor: Ky-Hyun Han
  • Patent number: 7582532
    Abstract: A method for fabricating a semiconductor device includes etching a predetermined portion of a substrate to form a first recess having a bottom middle portion roundly projected and bottom edge portions tapered to have a micro-trench profile; and etching the substrate beneath the first recess to form a second recess, the second recess being rounded and being wider than the first recess.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: September 1, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ky-Hyun Han, Seung-Bum Kim
  • Patent number: 7582560
    Abstract: A method for fabricating a semiconductor device includes preparing a substrate comprising a first surface and a second surface formed at a lower position than the first surface, forming an insulation layer over the substrate, etching the insulation layer to form a first contact hole exposing the first surface and a second contact hole having a larger depth than the first contact hole above the second surface, forming a first sacrificial layer over the insulation layer, the first contact hole, and the second contact hole, forming a second sacrificial layer over the substrate structure and filled in the first contact hole, exposing the first sacrificial layer at a bottom surface of the second contact hole while having the second sacrificial layer remain in the first contact hole, etching the first sacrificial layer, and etching the remaining insulation layer to expose the second surface.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: September 1, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ky-Hyun Han, Ki-Won Nam
  • Patent number: 7485557
    Abstract: A method for fabricating a semiconductor device having a flask type recess gate includes forming a hard mask pattern on a substrate, etching the substrate to a predetermined depth using the hard mask pattern to form a first recess pattern, forming a passivation layer on sidewalls of the first recess pattern and the hard mask pattern, etching a bottom surface of the first recess pattern exposed by the passivation layer to form a second recess pattern, oxidizing sidewalls of the second recess pattern to form a silicon oxide layer, removing the passivation layer and the silicon oxide layer in sequential order, and forming a gate pattern over an intended recess pattern including the first recess pattern and the second recess pattern.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: February 3, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ky-Hyun Han, Sang-Soo Park
  • Publication number: 20090001582
    Abstract: A semiconductor device includes a substrate, a gate dielectric layer over the substrate, a silicon electrode over the gate dielectric layer, wherein the silicon electrode comprises a damascene pattern, a diffusion barrier layer on a bottom and a sidewall of the damascene pattern, and a metal electrode over the diffusion barrier layer, wherein the metal electrode fills the damascene pattern.
    Type: Application
    Filed: December 12, 2007
    Publication date: January 1, 2009
    Applicant: Hyunix Semiconductor Inc.
    Inventors: Ky-Hyun HAN, Ki-Won Nam
  • Publication number: 20080242095
    Abstract: A method for fabricating a trench in a semiconductor device includes forming a mask pattern over a substrate, and etching the substrate to form a trench with a vertical profile, the etching performed at an etching rate of approximately 40 A/sec or less using an etching gas including a gas generating polymers
    Type: Application
    Filed: June 29, 2007
    Publication date: October 2, 2008
    Inventors: Ky-Hyun Han, Dong-Hyun Kim
  • Publication number: 20080242098
    Abstract: A method for forming a pattern in a semiconductor device includes forming an etch target layer over a substrate, forming a hard mask pattern over the etch target layer, and etching the etch target layer using the hard mask pattern as an etch mask and a gas mixture including a fluorine (F)-based gas and a bromine (Br)-based gas as an etch gas to form a target pattern.
    Type: Application
    Filed: June 28, 2007
    Publication date: October 2, 2008
    Inventors: Ki-Won Nam, Ky-Hyun Han
  • Publication number: 20080160778
    Abstract: A method for forming a pattern in a semiconductor device includes forming an etch target layer, forming a hard mask over the etch target layer, the hard mask including a multiple-layer stack structure comprising a bottom layer, a transformed layer, and an upper layer, wherein the transformed layer is formed by transforming a surface of the bottom layer. The hard mask and the etch target layer are etched.
    Type: Application
    Filed: June 28, 2007
    Publication date: July 3, 2008
    Inventors: Ki-Won Nam, Ky-Hyun Han
  • Publication number: 20080160765
    Abstract: A method for forming a semiconductor device includes forming an etch target layer, forming a sacrificial hard mask layer having a metal layer and a carbon-based material layer on the etch target layer, forming a photoresist pattern on the carbon-based material layer, etching the carbon-based material layer by the photoresist pattern until a remaining carbon-based material portion has a predetermined thickness, etching the remaining carbon-based material portion until a corresponding metal layer portion is exposed to form a carbon-based material pattern, and etching the metal layer by using the carbon-based material pattern to form a hard mask pattern for forming the pattern.
    Type: Application
    Filed: June 29, 2007
    Publication date: July 3, 2008
    Inventors: Jung-Seock Lee, Ky-Hyun Han
  • Publication number: 20080128799
    Abstract: A method for fabricating a semiconductor device includes etching a substrate to form a first recess having a micro trench, etching the substrate disposed under the first recess to form a second recess having a profile substantially vertical and a width greater than a portion of the first recess where no micro trench is formed, etching the substrate disposed under the second recess to form a third recess having a profile substantially spherical, and forming a gate pattern over a resultant recess including the first to third recesses.
    Type: Application
    Filed: June 26, 2007
    Publication date: June 5, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Hyun-Sik PARK, Ky-Hyun HAN
  • Publication number: 20080108216
    Abstract: A method for forming a contact in a semiconductor device includes opening a contact hole exposing a surface of a substrate, performing a first post treatment to form a rough portion at a bottom surface of the contact hole, and performing a second post treatment. The first post treatment includes using a fluorocarbon gas and the second post treatment includes using a nitrogen trifluoride (NF3) gas.
    Type: Application
    Filed: February 26, 2007
    Publication date: May 8, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Jung-Seock LEE, Ky-Hyun Han
  • Publication number: 20080081434
    Abstract: A method for forming an isolation structure in a semiconductor device includes preparing a semi-finished substrate including a trench. An oxide layer is formed over sidewalls of the trench. A multiple layer structure of liner layers is formed over the oxide layer. An insulation layer is formed over the multiple layer structure such that the insulation layer fills an inside of the trench. The insulation layer is planarized.
    Type: Application
    Filed: April 23, 2007
    Publication date: April 3, 2008
    Inventors: Ki-Won Nam, Ky-Hyun Han
  • Publication number: 20080079067
    Abstract: A recess gate of a semiconductor device includes: a substrate having a bulb-shaped recess pattern formed therein, wherein the bulb-shaped recess pattern includes a first ball pattern and a second ball pattern formed therein, the first ball pattern having a different diameter than the second ball pattern; a gate insulation layer formed over the bulb-shaped recess pattern and the substrate; and a conductive layer formed over the gate insulation layer and filling the bulb-shaped recess pattern.
    Type: Application
    Filed: December 27, 2006
    Publication date: April 3, 2008
    Inventors: Ky-Hyun Han, Ki-Won Nam
  • Publication number: 20080081448
    Abstract: A method for fabricating a semiconductor device includes forming an insulation layer, a first electrode layer, a second electrode layer, and a hard mask over a substrate, etching the second electrode layer to form second electrodes with recessed sidewalls, forming a passivation layer over a resultant surface profile provided after forming the second electrodes, performing an etch-back process on the passivation layer, and etching the first electrode layer exposed by the etch-back process to form first electrodes.
    Type: Application
    Filed: June 28, 2007
    Publication date: April 3, 2008
    Inventors: Jung-Seock Lee, Ky-Hyun Han
  • Patent number: 7345338
    Abstract: A recess gate of a semiconductor device includes: a substrate having a bulb-shaped recess pattern formed therein, wherein the bulb-shaped recess pattern includes a first ball pattern and a second ball pattern formed therein, the first ball pattern having a different diameter than the second ball pattern; a gate insulation layer formed over the bulb-shaped recess pattern and the substrate; and a conductive layer formed over the gate insulation layer and filling the bulb-shaped recess pattern.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: March 18, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ky-Hyun Han, Ki-Won Nam
  • Publication number: 20080064221
    Abstract: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate, etching the insulation layer using a hard mask pattern to form a contact hole, filling the contact hole with a conductive layer, etching the conductive layer to form a plug in the contact hole, removing the remaining hard mask pattern to expose an upper portion of the plug and have the upper portion protrude above the insulation layer, and forming a metal line over the protruding plug and around the upper portion of the plug.
    Type: Application
    Filed: December 28, 2006
    Publication date: March 13, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Ky-Hyun Han, Ki-Won Nam
  • Publication number: 20080003732
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of gate lines on a substrate, forming a first cell spacer on the gate lines, forming a second cell spacer on the first cell spacer, forming a buffer layer on the second cell spacer, and exposing the surface of the substrate by etching the buffer layer.
    Type: Application
    Filed: December 18, 2006
    Publication date: January 3, 2008
    Inventors: Ki-Won Nam, Ky-Hyun Han
  • Publication number: 20080003832
    Abstract: A recess pattern is formed in a substrate where an isolation structure is formed. Portions of the substrate are etched to remove a horn generated while forming the recess pattern. A gate insulation layer is formed over the recess pattern and the substrate. A gate structure is formed over the gate insulation layer, covering the recess pattern.
    Type: Application
    Filed: March 8, 2007
    Publication date: January 3, 2008
    Inventors: Ky-Hyun Han, Ki-Won Nam
  • Publication number: 20070287286
    Abstract: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate having a given structure, forming a hard mask pattern over the insulation layer, performing a main etch on the insulation layer with a high etch selectivity with respect to a hard mask pattern to form a preliminary contact hole, performing an overetch on the insulation layer with a low etch selectivity with respect to a hard mask pattern to form a contact hole, and forming a conductive layer and performing an etch-back process to form a contact filled in the contact hole.
    Type: Application
    Filed: December 29, 2006
    Publication date: December 13, 2007
    Inventors: Ki-Won Nam, Ky-Hyun Han