Patents by Inventor Ky-Hyun Han

Ky-Hyun Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070287293
    Abstract: A method for fabricating a semiconductor device includes preparing a substrate comprising a first surface and a second surface formed at a lower position than the first surface, forming an insulation layer over the substrate, etching the insulation layer to form a first contact hole exposing the first surface and a second contact hole having a larger depth than the first contact hole above the second surface, forming a first sacrificial layer over the insulation layer, the first contact hole, and the second contact hole, forming a second sacrificial layer over the substrate structure and filled in the first contact hole, exposing the first sacrificial layer at a bottom surface of the second contact hole while having the second sacrificial layer remain in the first contact hole, etching the first sacrificial layer, and etching the remaining insulation layer to expose the second surface.
    Type: Application
    Filed: March 12, 2007
    Publication date: December 13, 2007
    Inventors: Ky-Hyun Han, Ki-Won Nam
  • Publication number: 20070202710
    Abstract: A method for fabricating a semiconductor device includes forming a layer to be etched, forming a hard mask pattern over the layer, and etching the layer to form a pattern. The hard mask pattern has an atomic percentage of a silicon-hydrogen bond varying with a thickness of the hard mask pattern.
    Type: Application
    Filed: December 29, 2006
    Publication date: August 30, 2007
    Inventors: Ki-Won Nam, Ky-Hyun Han
  • Publication number: 20070202687
    Abstract: A method for fabricating a semiconductor device includes forming an insulation structure over a substrate structure including contact plugs, etching the insulation structure to form opening regions each of which has a lower opening portion having a critical dimension wider than an upper opening portion, and forming a conductive layer contacting the contact plugs inside the opening regions.
    Type: Application
    Filed: February 13, 2007
    Publication date: August 30, 2007
    Inventor: Ky-Hyun Han
  • Publication number: 20070197021
    Abstract: A method for fabricating a semiconductor device includes: forming a plurality of bit lines; forming an inter-layer insulation layer over the bit lines; etching the inter-layer insulation layer to form a storage node contact hole between the bit lines; forming spacers in a dual structure with different dielectric constants over sidewalls of the storage node contact hole; and forming a storage node contact plug filling the storage node contact hole.
    Type: Application
    Filed: November 9, 2006
    Publication date: August 23, 2007
    Inventors: Ki-Won Nam, Ky-Hyun Han
  • Publication number: 20070134869
    Abstract: A method for fabricating a semiconductor device includes etching a predetermined portion of a substrate to form a device isolation region, forming a barrier layer over the substrate and the device isolation region, selectively etching the barrier layer to expose a bottom surface of the device isolation region, etching the exposed bottom surface of the device isolation region using the barrier layer as an etch barrier, performing an isotropic etching process onto a bottom portion of the device isolation region, and forming a device isolation structure filled into the device isolation region.
    Type: Application
    Filed: June 29, 2006
    Publication date: June 14, 2007
    Inventors: Ky-Hyun Han, Ki-Won Nam
  • Publication number: 20070128842
    Abstract: A method for fabricating a semiconductor device includes: forming a plurality of conductive patterns with regionally different densities over a substrate; forming a first insulation layer over the conductive patterns; forming a second insulation layer having substantially the same etch selectivity as the first insulation layer and a better step coverage capability than the first insulation layer over the first insulation layer; oxidizing a predetermined portion of the second insulation layer to form a third insulation layer; and etching the third insulation layer, a remaining portion of the second insulation layer, and the first insulation layer to form spacers over sidewalls of the conductive patterns.
    Type: Application
    Filed: June 29, 2006
    Publication date: June 7, 2007
    Inventors: Ki-Won Nam, Ky-Hyun Han
  • Publication number: 20070123014
    Abstract: A method for fabricating a semiconductor device having a flask type recess gate includes forming a hard mask pattern on a substrate, etching the substrate to a predetermined depth using the hard mask pattern to form a first recess pattern, forming a passivation layer on sidewalls of the first recess pattern and the hard mask pattern, etching a bottom surface of the first recess pattern exposed by the passivation layer to form a second recess pattern, oxidizing sidewalls of the second recess pattern to form a silicon oxide layer, removing the passivation layer and the silicon oxide layer in sequential order, and forming a gate pattern over an intended recess pattern including the first recess pattern and the second recess pattern.
    Type: Application
    Filed: August 1, 2006
    Publication date: May 31, 2007
    Inventors: Ky-Hyun Han, Sang-Soo Park
  • Publication number: 20070105388
    Abstract: A method for fabricating a semiconductor device includes forming a mask pattern over a substrate; etching a certain portion of the substrate using the mask pattern as an etch mask to form a first recess having sidewalls; forming a polymer-based layer over the sidewalls of the first recess and a top surface of the mask pattern; etching the substrate beneath the first recess using the mask pattern and the polymer-based layer as an etch mask to form a second recess wider and more rounded than the first recess, the second recess and the first recess constituting a bulb-shaped recess; and forming a gate pattern over the bulb-shaped recess.
    Type: Application
    Filed: June 30, 2006
    Publication date: May 10, 2007
    Inventors: Jung-Seock Lee, Ky-Hyun Han
  • Publication number: 20070099383
    Abstract: A method for fabricating a semiconductor device includes etching a predetermined portion of a substrate to form a first recess having a bottom middle portion roundly projected and bottom edge portions tapered to have a micro-trench profile; and etching the substrate beneath the first recess to form a second recess, the second recess being rounded and being wider than the first recess.
    Type: Application
    Filed: June 30, 2006
    Publication date: May 3, 2007
    Inventors: Ky-Hyun Han, Seung-Bum Kim
  • Publication number: 20070099384
    Abstract: A method for fabricating a semiconductor device having a recess gate includes forming a hard mask pattern on a substrate, etching the substrate using the hard mask pattern as an etch barrier to form a recess pattern, forming a passivation layer protecting surfaces of the recess pattern, etching a bottom surface of the recess pattern while protecting sidewalls of the recess pattern, performing an isotropic etching process onto a bottom portion of the recess pattern, and forming a gate pattern partially buried into the recess pattern after the isotropic etching process is performed.
    Type: Application
    Filed: June 29, 2006
    Publication date: May 3, 2007
    Inventors: Ky-Hyun Han, Jung-Seock Lee