Abstract: Field reducing structures for transistor devices having Group III-nitride semiconductor structures are provided. In one example, a transistor device includes a nitrogen-polar (N-polar) Group III-nitride semiconductor structure. The transistor device includes a source contact, a drain contact, and a gate contact. The transistor device includes a field reducing structure operable to reduce an electric field in a region in the N-polar Group III-nitride semiconductor structure between the gate contact and the drain contact.

Abstract: A transistor device includes a semiconductor structure comprising a channel layer and a barrier layer, source and drain contacts on the semiconductor structure, and a conductive element in a recess in the barrier layer between the source and drain contacts. The barrier layer has a first thickness adjacent the source or drain contact, a second thickness at a floor of the recess between the conductive element and the channel layer, and the first thickness is about 1.2 times to 4 times greater than the second thickness. Related methods of fabrication using a looped recess process are also discussed.

Abstract: A high electron mobility transistor comprises a semiconductor layer structure that includes a channel layer and a barrier layer and source and drain contacts on the semiconductor layer structure. A gate contact and a multi-layer passivation structure are provided on the semiconductor layer structure between the source contact and the drain contact. The multi-layer passivation structure comprises at least first and second silicon nitride layers that have different material compositions. A spacer passivation layer is provided on sidewalls of the first and second silicon nitride layers. A material composition of the spacer passivation layer is different than a material composition of at least one of the layers of the multi-layer passivation structure.

Abstract: A transistor device includes a semiconductor structure, source and drain contacts on the semiconductor structure, a gate on the semiconductor structure between the source and drain contacts, and a surface passivation layer on the semiconductor structure between the gate and the source or drain contact. The surface passivation layer includes an opening therein that exposes a first region of the semiconductor structure for processing the first region differently than a second region of the semiconductor structure adjacent the gate. Related devices and fabrication methods are also discussed.

Abstract: A transistor device includes a first unit subcell including having a first active region width extending in a first direction, and a second unit subcell having a second active region width extending in the first direction and arranged adjacent the first unit subcell in the first direction. The first unit subcell and the second unit subcell share a common drain contact and have separate gate contacts that are aligned in the first direction. Each unit subcell includes a field plate that is connected to a source contact outside the active region and that does not cross over the gate contact.

Abstract: Cost reduction of semiconductor transistors is achieved by reduction in the amount of expensive metal, such as gold, used to form metal contacts and conductive paths in integrated circuits. A semiconductor transistor structure is formed, and ohmic source and drain terminals formed thereon. A gate terminal is formed over an insulating layer in the active area between the source and drain terminals. A field plate is formed at least partially over the gate terminal. Interface layers are deposited over the source and drain terminals, using the field plate metal structure, such as in the same processing step as field plate deposition. Metal contacts are then deposited over the interface layers. The metal contacts are considerably thinner than required in the prior art to support high current densities. Because gold is often used in the metal contacts, their smaller size reduces costs by requiring less gold to achieve the same performance.

Abstract: A transistor device includes a semiconductor structure comprising a channel layer and a barrier layer; source and drain contacts on the semiconductor structure; and a gate on the semiconductor structure between the source and drain contacts. A first portion of the barrier layer extending between the source or drain contact and the gate has a first thickness, a second portion of the barrier layer between the gate and the channel layer has a second thickness, and the first thickness is about 1.5 times to 4 times greater than the second thickness. Related methods of fabrication using a looped recess process are also discussed.

Abstract: A multi-gate switch field effect transistor, FET, according to some embodiments includes a semiconductor structure, a source contact on the semiconductor structure, and a drain contact on the semiconductor structure. The multi-gate switch FET further includes a first gate on the semiconductor structure between the source contact and the drain contact; and a second gate on the semiconductor structure adjacent to the first gate and between the source contact and the drain contact. The multi-gate switch FET further includes a conducting region in the semiconductor structure between the first gate and the second gate.

Abstract: A transistor includes a group III-Nitride channel layer; a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer having a higher bandgap than a bandgap of the group III-Nitride channel layer; a low resistance contact layer on the group III-Nitride barrier layer and/or on the group III-Nitride channel layer; a source electrically coupled to the group III-Nitride barrier layer. A drain electrically coupled to the group III-Nitride barrier layer; and a gate on the group III-Nitride barrier layer. Additionally, at least one of the drain and the source are arranged on the low resistance contact layer.

Abstract: A transistor includes a group III-Nitride channel layer; a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer having a higher bandgap than a bandgap of the group III-Nitride channel layer; a low resistance contact layer on the group III-Nitride barrier layer and/or on the group III-Nitride channel layer; a source electrically coupled to the group III-Nitride barrier layer. A drain electrically coupled to the group III-Nitride barrier layer; and a gate on the group III-Nitride barrier layer. Additionally, at least one of the drain and the source are arranged on the low resistance contact layer.

Abstract: A transistor device according to some embodiments includes a semiconductor barrier layer, a surface dielectric layer on the semiconductor barrier layer, and a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The device includes an interlayer dielectric layer on the surface dielectric layer that extends over the gate and into the aperture in the surface dielectric layer, and a multiple-stepped field plate on the interlayer dielectric layer. The multiple-stepped field plate is laterally spaced apart from the gate. A recessed portion of the multiple-stepped field plate is above the aperture in the surface dielectric layer, and the multiple-stepped field plate includes a first step adjacent the recessed portion of the field plate on a side of the field plate opposite the gate, and a second step adjacent the first step.

Abstract: Semiconductor devices are provided. In one example, the semiconductor device includes a wide bandgap semiconductor structure. The semiconductor device includes a metal structure on the wide bandgap semiconductor structure. The metal structure has a metal layer. The metal layer has a metal selected from the group consisting of ruthenium, osmium, rhodium, or iridium.

Abstract: A HEMT transistor has a semiconductor layer structure that comprises a Group III nitride-based channel layer and a higher bandgap Group III nitride-based barrier layer on the channel layer. A gate finger and first and second source/drain contacts are provided on the semiconductor layer structure. A first source/drain region is provided in the semiconductor layer structure that includes a first implanted region that is underneath the first source/drain contact and a first auxiliary implanted region. A depth of the first implanted region is at least twice a depth of the first auxiliary implanted a region. The first source/drain region extends inwardly a first distance from a lower edge of an inner sidewall of the first source/drain contact, and extends outwardly a second smaller distance from a lower edge of an outer sidewall of the first source/drain contact.

Abstract: A semiconductor device includes a substrate having an upper surface including a recess region, a semiconductor structure on the substrate, a portion of the semiconductor structure within the recess region, and a gate contact, a drain contact, and a source contact on the semiconductor structure. The recess region does not vertically overlap the drain contact or the source contact.

Abstract: A semiconductor device includes a semiconductor structure comprising first and second semiconductor layers having different bandgaps, first and second contacts on the semiconductor structure and free of a gate structure therebetween, and a resistor comprising a portion of the semiconductor structure that electrically connects the first and second contacts. The portion of the semiconductor structure may be a second portion of the second semiconductor layer that is recessed in thickness relative to a first portion thereof, and/or may include a passivation layer in direct contact with the second semiconductor layer. Related devices, packages, and fabrication methods are discussed.

Abstract: Semiconductor devices are provided. In one example, a semiconductor device includes a Group III-nitride semiconductor structure. The semiconductor device includes a first contact on the Group III-nitride semiconductor structure. The semiconductor device includes a second contact on the Group III-nitride semiconductor structure. The second contact is spaced apart from the first contact. The Group III-nitride semiconductor structure includes a plurality of channel structures extending in a length direction between the first contact and the second contact. The semiconductor device includes an isolation implant region extending along at least a portion of a length of at least one of the plurality of channel structures. The isolation implant region comprises implanted dopants.

Abstract: A thermally conductive interposer includes an interposer substrate having a first substrate surface and a second substrate surface. The first substrate surface being configured to be attached to a first device component. The second substrate surface being configured to be attached to a second device component. The interposer substrate being configured to support the second device component on the first device component and integrate the first device component and the second device component within a microelectronic device. Further, the interposer substrate is configured to transfer heat between the first device component and the second device component; and the interposer substrate is configured to be electrically nonconductive.

Abstract: Semiconductor devices are provided. In one example, a semiconductor device includes a Group III-nitride semiconductor structure. The semiconductor device may include a gate contact on the Group III-nitride semiconductor structure. The semiconductor device may include a field plate overlapping the Group III-nitride semiconductor structure. The semiconductor device may include a thermally conductive passivation layer overlapping the gate contact. The thermally conductive passivation layer may be between the field plate and the Group III-nitride semiconductor structure. The thermally conductive passivation layer may contact the Group III-nitride semiconductor structure. The thermally conductive passivation layer may have a thermal conductivity of at least about 80 W/(m·k).

Abstract: Semiconductor devices with reduced contact resistance of ohmic contacts are provided. In one example, the semiconductor device includes a Group III-nitride semiconductor structure. The Group III-nitride semiconductor structure includes a channel layer and a barrier layer on the channel layer. The semiconductor device includes an implanted region extending into the channel layer. The implanted region includes a distribution of implanted dopants. The semiconductor device includes a recess in the implanted region. The recess extends through the barrier layer into the channel layer. The semiconductor device includes an ohmic contact within the recess.

Abstract: A transistor includes a semiconductor layer and a channel region. The transistor further includes a first doped contact region in the semiconductor layer and adjacent the channel region. The transistor further includes a first ohmic contact including an interface region comprising a first interface length between the first ohmic contact and the first doped contact region larger than a length of the interface region.