Abstract: A transistor includes a group III-Nitride channel layer; a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer having a higher bandgap than a bandgap of the group III-Nitride channel layer; a low resistance contact layer on the group III-Nitride barrier layer and/or on the group III-Nitride channel layer; a source electrically coupled to the group III-Nitride barrier layer. A drain electrically coupled to the group III-Nitride barrier layer; and a gate on the group III-Nitride barrier layer. Additionally, at least one of the drain and the source are arranged on the low resistance contact layer.

Abstract: A transistor includes a group III-Nitride channel layer; a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer having a higher bandgap than a bandgap of the group III-Nitride channel layer; a low resistance contact layer on the group III-Nitride barrier layer and/or on the group III-Nitride channel layer; a source electrically coupled to the group III-Nitride barrier layer. A drain electrically coupled to the group III-Nitride barrier layer; and a gate on the group III-Nitride barrier layer. Additionally, at least one of the drain and the source are arranged on the low resistance contact layer.

Abstract: A transistor device according to some embodiments includes a semiconductor barrier layer, a surface dielectric layer on the semiconductor barrier layer, and a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The device includes an interlayer dielectric layer on the surface dielectric layer that extends over the gate and into the aperture in the surface dielectric layer, and a multiple-stepped field plate on the interlayer dielectric layer. The multiple-stepped field plate is laterally spaced apart from the gate. A recessed portion of the multiple-stepped field plate is above the aperture in the surface dielectric layer, and the multiple-stepped field plate includes a first step adjacent the recessed portion of the field plate on a side of the field plate opposite the gate, and a second step adjacent the first step.

Abstract: Semiconductor devices are provided. In one example, the semiconductor device includes a wide bandgap semiconductor structure. The semiconductor device includes a metal structure on the wide bandgap semiconductor structure. The metal structure has a metal layer. The metal layer has a metal selected from the group consisting of ruthenium, osmium, rhodium, or iridium.

Abstract: A HEMT transistor has a semiconductor layer structure that comprises a Group III nitride-based channel layer and a higher bandgap Group III nitride-based barrier layer on the channel layer. A gate finger and first and second source/drain contacts are provided on the semiconductor layer structure. A first source/drain region is provided in the semiconductor layer structure that includes a first implanted region that is underneath the first source/drain contact and a first auxiliary implanted region. A depth of the first implanted region is at least twice a depth of the first auxiliary implanted a region. The first source/drain region extends inwardly a first distance from a lower edge of an inner sidewall of the first source/drain contact, and extends outwardly a second smaller distance from a lower edge of an outer sidewall of the first source/drain contact.

Abstract: A semiconductor device includes a substrate having an upper surface including a recess region, a semiconductor structure on the substrate, a portion of the semiconductor structure within the recess region, and a gate contact, a drain contact, and a source contact on the semiconductor structure. The recess region does not vertically overlap the drain contact or the source contact.

Abstract: Semiconductor devices are provided. In one example, a semiconductor device includes a Group III-nitride semiconductor structure. The semiconductor device includes a first contact on the Group III-nitride semiconductor structure. The semiconductor device includes a second contact on the Group III-nitride semiconductor structure. The second contact is spaced apart from the first contact. The Group III-nitride semiconductor structure includes a plurality of channel structures extending in a length direction between the first contact and the second contact. The semiconductor device includes an isolation implant region extending along at least a portion of a length of at least one of the plurality of channel structures. The isolation implant region comprises implanted dopants.

Abstract: A semiconductor device includes a semiconductor structure comprising first and second semiconductor layers having different bandgaps, first and second contacts on the semiconductor structure and free of a gate structure therebetween, and a resistor comprising a portion of the semiconductor structure that electrically connects the first and second contacts. The portion of the semiconductor structure may be a second portion of the second semiconductor layer that is recessed in thickness relative to a first portion thereof, and/or may include a passivation layer in direct contact with the second semiconductor layer. Related devices, packages, and fabrication methods are discussed.

Abstract: Semiconductor devices are provided. In one example, a semiconductor device includes a Group III-nitride semiconductor structure. The semiconductor device may include a gate contact on the Group III-nitride semiconductor structure. The semiconductor device may include a field plate overlapping the Group III-nitride semiconductor structure. The semiconductor device may include a thermally conductive passivation layer overlapping the gate contact. The thermally conductive passivation layer may be between the field plate and the Group III-nitride semiconductor structure. The thermally conductive passivation layer may contact the Group III-nitride semiconductor structure. The thermally conductive passivation layer may have a thermal conductivity of at least about 80 W/(m·k).

Abstract: A thermally conductive interposer includes an interposer substrate having a first substrate surface and a second substrate surface. The first substrate surface being configured to be attached to a first device component. The second substrate surface being configured to be attached to a second device component. The interposer substrate being configured to support the second device component on the first device component and integrate the first device component and the second device component within a microelectronic device. Further, the interposer substrate is configured to transfer heat between the first device component and the second device component; and the interposer substrate is configured to be electrically nonconductive.

Abstract: Semiconductor devices with reduced contact resistance of ohmic contacts are provided. In one example, the semiconductor device includes a Group III-nitride semiconductor structure. The Group III-nitride semiconductor structure includes a channel layer and a barrier layer on the channel layer. The semiconductor device includes an implanted region extending into the channel layer. The implanted region includes a distribution of implanted dopants. The semiconductor device includes a recess in the implanted region. The recess extends through the barrier layer into the channel layer. The semiconductor device includes an ohmic contact within the recess.

Abstract: A transistor includes a semiconductor layer and a channel region. The transistor further includes a first doped contact region in the semiconductor layer and adjacent the channel region. The transistor further includes a first ohmic contact including an interface region comprising a first interface length between the first ohmic contact and the first doped contact region larger than a length of the interface region.

Abstract: A transistor device includes a semiconductor body and a non-ohmic contact on the semiconductor body. The non-ohmic contact includes a phonon scattering layer on the semiconductor body, a protection layer on a surface of the phonon scattering layer opposite the semiconductor body, and a contact layer on a surface of the protection layer opposite the phonon scattering layer. The phonon scattering layer has a work function in a range of about 4.5 eV to about 5.7 eV and a melting point in a range of about 1550° C. to about 3200° C.

Abstract: Field reducing structures for transistor devices having Group III-nitride semiconductor structures are provided. In one example, a transistor device includes a nitrogen-polar (N-polar) Group III-nitride semiconductor structure. The transistor device includes a source contact, a drain contact, and a gate contact. The transistor device includes a field reducing structure operable to reduce an electric field in a region in the N-polar Group III-nitride semiconductor structure between the gate contact and the drain contact.

Abstract: Semiconductor device having nitrogen-polar (N-polar) Group III-nitride structures are provided. In one example, a semiconductor device may include an N-polar Group III-nitride semiconductor structure. The N-polar Group III-nitride semiconductor structure may have a first region and a second region. The N-polar Group III-nitride semiconductor structure may have a first surface and a second surface opposing the first surface. The second surface may be a planar surface. The semiconductor device may include an isolation implant region extending from the second surface into the N-polar Group III-nitride semiconductor structure to a depth sufficient to provide electrical isolation between the first region and the second region of the N-polar Group III-nitride semiconductor structure.

Abstract: Semiconductor devices having nitrogen-polar (N-polar) Group III-nitride semiconductor structures are provided. In one example, a semiconductor device may include a nitrogen polar (N-polar) Group III-nitride semiconductor structure. The N-polar Group III-nitride semiconductor structure may have a first surface and a second surface opposing the first surface. The semiconductor device may include an electrode. The semiconductor device may include a low-k dielectric layer located between the first surface of the N-polar Group III-nitride semiconductor structure and at least a portion of the electrode. The low-k dielectric layer may have a dielectric constant of less than about 3.9. In some examples, the N-polar Group III-nitride semiconductor structure may include a trench extending at least partially into one or more cap layers of the N-polar Group III-nitride semiconductor structure.

Abstract: Semiconductor devices are provided. In one example, a semiconductor device includes a substrate. The semiconductor device includes a nitrogen-polar (N-polar) Group III-nitride semiconductor structure on the substrate. The semiconductor device includes a via passing through the substrate and the N-polar Group III-nitride semiconductor structure. A cross-sectional profile of the via changes at an interface between the substrate and the N-polar Group III-nitride semiconductor structure.

Abstract: Semiconductor devices are provided. In one example, a semiconductor device includes a substrate. The semiconductor device includes a polarity inverting layer on the substrate. The semiconductor device includes a nitrogen-polar (N-Polar) Group III-nitride semiconductor structure on the polarity inverting layer.

Abstract: A method of forming a high electron mobility transistor (HEMT) includes: providing a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate; forming a first insulating layer on the barrier layer; and forming a gate contact, a source contact, and a drain contact on the barrier layer. An interface between the first insulating layer and the barrier layer comprises a modified interface region on a drain access region and/or a source access region of the semiconductor structure such that a sheet resistance of the drain access region and/or the source access region is between 300 and 400 ?/sq.

Abstract: A transistor device includes a semiconductor structure having an implanted region adjacent a surface thereof; and a source/drain contact including an ohmic contact portion on the implanted region of the semiconductor structure. The implanted region laterally extends beyond the ohmic contact portion by less than about 0.8 microns, e.g., by less than about 0.2 microns or such that a boundary of the implanted region is substantially aligned with an edge of the ohmic contact portion. Related fabrication methods are also discussed.