Abstract: A transistor device includes a substrate, a semiconductor structure on the substrate, a metallization layer comprising a non-planar surface on a surface of the semiconductor structure, a non-planar encapsulation layer on the non-planar surface of the metallization layer, the non-planar encapsulation layer comprising a non-planar encapsulant surface that is opposite the non-planar surface, and a self-planarizing encapsulation layer on the non-planar encapsulation layer and comprising a planarized surface that is opposite the non-planar encapsulant surface.

Abstract: A semiconductor die includes a semiconductor body having a gate, a source contact, and a drain contact thereon, a metal contact structure on the semiconductor body and electrically connected to the gate, the source contact, or the drain contact, and an encapsulation structure. The encapsulation structure includes first and second encapsulation layers of respective non-conductive materials stacked on the metal contact structure, and an opening extending therethrough to expose the metal contact structure. The opening includes a sidewall having a substantially continuous slope that extends through the first and second encapsulation layers to the metal contact structure. Related devices and fabrication methods are also discussed.

Abstract: A transistor device includes a semiconductor structure, source and drain contacts on the semiconductor structure, a gate on the semiconductor structure between the source and drain contacts, and a surface passivation layer on the semiconductor structure between the gate and the source or drain contact. The surface passivation layer includes an opening therein that exposes a first region of the semiconductor structure for processing the first region differently than a second region of the semiconductor structure adjacent the gate. Related devices and fabrication methods are also discussed.

Abstract: A method of forming a high electron mobility transistor (HEMT) includes: providing a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate; forming a first insulating layer on the barrier layer; and forming a gate contact, a source contact, and a drain contact on the barrier layer. An interface between the first insulating layer and the barrier layer comprises a modified interface region on a drain access region and/or a source access region of the semiconductor structure such that a sheet resistance of the drain access region and/or the source access region is between 300 and 400 ?/sq.

Abstract: A GaN-based high electron mobility transistor (HEMT) device includes a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate, a drain contact and a source contact on the barrier layer, and a gate contact on the barrier layer between the drain contact and the source contact. A sheet resistance of a drain access region and/or a source access region of the semiconductor structure is between 300 and 400 ?/sq.

Abstract: A transistor device includes a semiconductor layer, a surface dielectric layer on the semiconductor layer, and at least a portion of a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The transistor device includes an interlayer dielectric layer on the surface dielectric layer, and a field plate on the interlayer dielectric layer. The field plate is laterally spaced apart from the gate, and at least a portion of the field plate includes a recessed portion above the aperture in the surface dielectric layer.

Abstract: A transistor device includes a first unit subcell including having a first active region width extending in a first direction, and a second unit subcell having a second active region width extending in the first direction and arranged adjacent the first unit subcell in the first direction. The first unit subcell and the second unit subcell share a common drain contact and have separate gate contacts that are aligned in the first direction. Each unit subcell includes a field plate that is connected to a source contact outside the active region and that does not cross over the gate contact.

Abstract: A transistor device according to some embodiments includes a semiconductor barrier layer, a surface dielectric layer on the semiconductor barrier layer, and a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The device includes an interlayer dielectric layer on the surface dielectric layer that extends over the gate and into the aperture in the surface dielectric layer, and a multiple-stepped field plate on the interlayer dielectric layer. The multiple-stepped field plate is laterally spaced apart from the gate. A recessed portion of the multiple-stepped field plate is above the aperture in the surface dielectric layer, and the multiple-stepped field plate includes a first step adjacent the recessed portion of the field plate on a side of the field plate opposite the gate, and a second step adjacent the first step.

Abstract: A gallium nitride-based RF transistor amplifier comprises a semiconductor layer structure comprising a barrier layer on a channel layer, first and second source/drain regions in the semiconductor layer structure, first and second source/drain contacts on the respective first and second source/drain regions, and a longitudinally-extending gate finger that is between the first and second source/drain contacts. The first and second source/drain contacts each has an inner sidewall that faces the gate finger and an opposed outer sidewall. The first source/drain region extends a first distance from a lower edge of the inner sidewall of the first source/drain contact towards the second source/drain region along a transverse axis that extends parallel to a plane defined by the upper surface of the semiconductor layer structure, and extends a second, smaller distance from a lower edge of the outer sidewall of the first source/drain contact away from the second source/drain region.

Abstract: A transistor device includes a semiconductor layer, source and drain contacts on the semiconductor layer, a gate contact on the semiconductor layer between the source and drain contacts, and a field plate over the semiconductor layer between the gate contact and the drain contact. The transistor device includes a first electrical connection between the field plate and the source contact that is outside an active region of the transistor device, and a second electrical connection between the field plate and the source contact.

Abstract: A transistor device includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, a source contact and a drain contact on the barrier layer, an insulating layer on the semiconductor layer between the source contact and the drain contact, and a gate contact on the insulating layer. The gate contact includes a central portion that extends through the insulating layer and contacts the barrier layer and a drain side wing that extends laterally from the central portion of the gate toward the drain contact by a distance ?D. The drain side wing of the gate contact is spaced apart from the barrier layer by a distance d1 that is equal to a thickness of the insulating layer. The distance ?D is less than about 0.3 ?m, and the distance d1 is less than about 80 nm.

Abstract: A transistor device includes a semiconductor layer, a surface dielectric layer on the semiconductor layer, and at least a portion of a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The transistor device includes an interlayer dielectric layer on the surface dielectric layer, and a field plate on the interlayer dielectric layer. The field plate is laterally spaced apart from the gate, and at least a portion of the field plate includes a recessed portion above the aperture in the surface dielectric layer.

Abstract: A high-electron mobility transistor (HEMT) that includes a substrate, a group III-Nitride channel layer on the substrate, a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer that includes a higher bandgap than a bandgap of the group III-Nitride channel layer, a source electrically coupled to the group III-Nitride barrier layer, a gate electrically coupled to the group III-Nitride barrier layer, and a drain electrically coupled to the group III-Nitride barrier layer. The source and/or the drain are structured and arranged to extend through the group III-Nitride barrier layer into the group III-Nitride channel layer.

Abstract: A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.

Abstract: A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.

Abstract: A high electron mobility transistor (HEMT) includes a substrate comprising a first surface and a second surface on opposing sides of the substrate, a channel layer on the first surface of the substrate opposite the substrate, a barrier layer on the channel layer, a source contact comprising a first ohmic contact on an upper surface of the barrier layer, and a via extending from the second surface of the substrate to the first ohmic contact.

Abstract: A packaged electronic circuit includes a substrate having an upper surface, a first metal layer on the upper surface of the substrate, a first polymer layer on the first metal layer opposite the substrate, a second metal layer on the first polymer layer opposite the first metal layer, a dielectric layer on the first polymer layer and at least a portion of the second metal layer and a second polymer layer on the dielectric layer.

Abstract: A high electron mobility transistor (HEMT) includes a substrate comprising a first surface and a second surface on opposing sides of the substrate, a channel layer on the first surface of the substrate opposite the substrate, a barrier layer on the channel layer, a source contact comprising a first ohmic contact on an upper surface of the barrier layer, and a via extending from the second surface of the substrate to the first ohmic contact.

Abstract: A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1 DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.

Abstract: A packaged electronic circuit includes a substrate having an upper surface, a first metal layer on the upper surface of the substrate, a first polymer layer on the first metal layer opposite the substrate, a second metal layer on the first polymer layer opposite the first metal layer, a dielectric layer on the first polymer layer and at least a portion of the second metal layer and a second polymer layer on the dielectric layer.