Patents by Inventor Kyong-Ha Lee
Kyong-Ha Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20140254287Abstract: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.Type: ApplicationFiled: May 22, 2014Publication date: September 11, 2014Applicant: SK HYNIX INC.Inventor: Kyong Ha LEE
-
Patent number: 8699276Abstract: A semiconductor memory device including a first edge region for receiving a write command through a first pad portion to generate a column enable signal used in creation of a column selection signal; a second edge region including a data transmission control circuit capable of receiving an input data and a data strobe signal through a second pad portion and capable of receiving an address signal from the first pad portion to generate and output transmission data, the data transmission control circuit capable of outputting the column enable signal transmitted from the first edge region; and a core region including a column control portion that is capable of processing the transmission data in response to the column enable signal outputted from the second edge region to send the transmission data to bit lines electrically connected to memory cells.Type: GrantFiled: August 22, 2012Date of Patent: April 15, 2014Assignee: SK Hynix Inc.Inventor: Kyong Ha Lee
-
Publication number: 20130223160Abstract: A semiconductor memory device including a first edge region for receiving a write command through a first pad portion to generate a column enable signal used in creation of a column selection signal; a second edge region including a data transmission control circuit capable of receiving an input data and a data strobe signal through a second pad portion and capable of receiving an address signal from the first pad portion to generate and output transmission data, the data transmission control circuit capable of outputting the column enable signal transmitted from the first edge region; and a core region including a column control portion that is capable of processing the transmission data in response to the column enable signal outputted from the second edge region to send the transmission data to bit lines electrically connected to memory cells.Type: ApplicationFiled: August 22, 2012Publication date: August 29, 2013Applicant: SK hynix Inc.Inventor: Kyong Ha LEE
-
Patent number: 8520466Abstract: The internal command generation circuit includes a burst pulse generation unit and a pulse shifting unit. The burst pulse generation unit is configured to receive a command for a read or write operation, and generate a first burst pulse. The pulse shifting unit is configured to shift the first burst pulse and generate an internal command.Type: GrantFiled: July 27, 2012Date of Patent: August 27, 2013Assignee: SK Hynix Inc.Inventor: Kyong Ha Lee
-
Patent number: 8358558Abstract: An address control circuit is presented for use in reducing a skew in a write operation mode. The address control circuit includes a read column address control circuit and a write column address control circuit. The read column address control circuit is configured to generate a read column address from an address during a first burst period for a read operation mode. The write column address control circuit is configured to generate a write column address from the address during a second burst period for a write operation mode.Type: GrantFiled: June 28, 2010Date of Patent: January 22, 2013Assignee: Hynix Semiconductor Inc.Inventors: Kyong Ha Lee, Joo Hyeon Lee
-
Publication number: 20120294106Abstract: The internal command generation circuit includes a burst pulse generation unit and a pulse shifting unit. The burst pulse generation unit is configured to receive a command for a read or write operation, and generate a first burst pulse. The pulse shifting unit is configured to shift the first burst pulse and generate an internal command.Type: ApplicationFiled: July 27, 2012Publication date: November 22, 2012Applicant: SK HYNIX INC.Inventor: Kyong Ha Lee
-
Patent number: 8254202Abstract: The internal command generation circuit includes a burst pulse generation unit and a pulse shifting unit. The burst pulse generation unit is configured to receive a command for a read or write operation, and generate a first burst pulse. The pulse shifting unit is configured to shift the first burst pulse and generate an internal command.Type: GrantFiled: June 30, 2010Date of Patent: August 28, 2012Assignee: Hynix Semiconductor Inc.Inventor: Kyong Ha Lee
-
Patent number: 8233348Abstract: The bank active signal generation circuit comprises a decoded signal generator and an active signal generator. The decoded signal generator generates decoded signals from a first bank access signal, a second bank access signal and a row address signal in response to when a prefetch signal at a first mode. The decoded signal generator also generates decoded signals from the first bank access signal, the second bank access signal, and a third bank access signal in response when the prefetch signal at a second mode. The active signal generator generates bank active signals in response to receiving the decoded signals, an active pulse and a precharge pulse.Type: GrantFiled: December 29, 2009Date of Patent: July 31, 2012Assignee: Hynix Semiconductor Inc.Inventor: Kyong Ha Lee
-
Publication number: 20120008452Abstract: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.Type: ApplicationFiled: September 23, 2011Publication date: January 12, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Kyong Ha LEE
-
Patent number: 8068383Abstract: A semiconductor IC in which a least significant bit of an external address signal is fixed to a signal level, the semiconductor integrated circuit includes an address control circuit configured to produce a carry signal, when a test mode signal is activated, in response to a column command signal and output an address signal, which is sequentially increased from an initial internal address signal, by latching the external address signal as the initial internal address signal and combining the latched initial internal address signal and the carry signal.Type: GrantFiled: December 17, 2008Date of Patent: November 29, 2011Assignee: Hynix Semiconductor Inc.Inventor: Kyong Ha Lee
-
Patent number: 8050137Abstract: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.Type: GrantFiled: June 29, 2009Date of Patent: November 1, 2011Assignee: Hynix Semiconductor Inc.Inventor: Kyong Ha Lee
-
Patent number: 8027222Abstract: A burst mode control unit includes a burst period signal generation unit for generating a burst period signal which is enabled during a burst mode operation period, a burst pulse generation unit for generating a burst pulse, which is generated at every predetermined number of cycles during the enabled period of the burst period signal, in response to a read command and a write command, and a column access signal generation unit for receiving the burst signal and a clock signal and generating a column access signal which controls input and output of data during the burst mode operation period.Type: GrantFiled: June 4, 2009Date of Patent: September 27, 2011Assignee: Hynix Semiconductor Inc.Inventor: Kyong Ha Lee
-
Patent number: 8023357Abstract: A semiconductor memory includes an address converting circuit which latches an address and a bank signal and generates a latch address for activating a data access path of a second bank group, and converts the latch address according to a level of the bank signal and generates a variable address for activating a data access path of a first bank group, a first column decoder which decodes the variable address and generates a first output enable signal for activating the data access path of the first bank group, and a second column decoder which decodes the latch address and generates a second output enable signal for activating the data access path of the second bank group.Type: GrantFiled: June 30, 2009Date of Patent: September 20, 2011Assignee: Hynix Semiconductor Inc.Inventor: Kyong Ha Lee
-
Patent number: 7986574Abstract: A data input circuit comprises a sensing control unit which delays an internal write command by a predetermined period and generates a sense amplifier enable signal in response to a first clock signal, and a data sensing unit which senses align data and transfers the sensed data to a global line in response to the sense amplifier enable signal, wherein the sense amplifier enable signal is enabled at a time point when the align data is inputted in the data sensing unit.Type: GrantFiled: June 26, 2009Date of Patent: July 26, 2011Assignee: Hynix Semiconductor Inc.Inventor: Kyong Ha Lee
-
Publication number: 20110128811Abstract: The internal command generation circuit includes a burst pulse generation unit and a pulse shifting unit. The burst pulse generation unit is configured to receive a command for a read or write operation, and generate a first burst pulse. The pulse shifting unit is configured to shift the first burst pulse and generate an internal command.Type: ApplicationFiled: June 30, 2010Publication date: June 2, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Kyong Ha LEE
-
Publication number: 20110110176Abstract: An address control circuit is presented for use in reducing a skew in a write operation mode. The address control circuit includes a read column address control circuit and a write column address control circuit. The read column address control circuit is configured to generate a read column address from an address during a first burst period for a read operation mode. The write column address control circuit is configured to generate a write column address from the address during a second burst period for a write operation mode.Type: ApplicationFiled: June 28, 2010Publication date: May 12, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyong Ha LEE, Joo Hyeon LEE
-
Publication number: 20110075502Abstract: The bank active signal generation circuit comprises a decoded signal generator and an active signal generator. The decoded signal generator generates decoded signals from a first bank access signal, a second bank access signal and a row address signal in response to when a prefetch signal at a first mode. The decoded signal generator also generates decoded signals from the first bank access signal, the second bank access signal, and a third bank access signal in response when the prefetch signal at a second mode. The active signal generator generates bank active signals in response to receiving the decoded signals, an active pulse and a precharge pulse.Type: ApplicationFiled: December 29, 2009Publication date: March 31, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Kyong Ha LEE
-
Patent number: 7911868Abstract: A self-refresh period measurement circuit of a semiconductor device is disclosed, herein which includes a period measurement start signal generator configured to receive a self-refresh signal and an oscillation signal, to allow a self-refresh operation to be performed, and generate a period measurement start signal, to set the time that the oscillation signal is enabled, and a refresh period output unit configured to receive the period measurement start signal and the oscillation signal, and generate a refresh period output signal that is enabled for a period from the time that the period measurement start signal is enabled to a time that the oscillation signal is enabled.Type: GrantFiled: January 13, 2009Date of Patent: March 22, 2011Assignee: Hynix Semiconductor Inc.Inventor: Kyong Ha Lee
-
Publication number: 20100246310Abstract: A semiconductor memory includes an address converting circuit which latches an address and a bank signal and generates a latch address for activating a data access path of a second bank group, and converts the latch address according to a level of the bank signal and generates a variable address for activating a data access path of a first bank group, a first column decoder which decodes the variable address and generates a first output enable signal for activating the data access path of the first bank group, and a second column decoder which decodes the latch address and generates a second output enable signal for activating the data access path of the second bank group.Type: ApplicationFiled: June 30, 2009Publication date: September 30, 2010Inventor: Kyong Ha Lee
-
Patent number: 7800966Abstract: A precharge control circuit includes a precharge control unit and a precharge unit. The precharge control unit controls and outputs a precharge signal in response to a read command signal, a write command signal, and a first signal. The precharge unit precharges local input/output lines in response to a signal output from the precharge control unit.Type: GrantFiled: December 12, 2007Date of Patent: September 21, 2010Assignee: Hynix Semiconductor Inc.Inventors: Kyong Ha Lee, Jong Won Lee