Abstract: A data input circuit comprises a sensing control unit which delays an internal write command by a predetermined period and generates a sense amplifier enable signal in response to a first clock signal, and a data sensing unit which senses align data and transfers the sensed data to a global line in response to the sense amplifier enable signal, wherein the sense amplifier enable signal is enabled at a time point when the align data is inputted in the data sensing unit.

Abstract: A self-refresh period measurement circuit of a semiconductor device is disclosed, herein which includes a delay means for delaying the received oscillation signal by a unit self-refresh period to output a first delayed oscillation signal, and delaying the received oscillation signal to output a third delayed oscillation signal, a first period measurement start signal generator for generating a first period measurement start signal for setting a time that the oscillation signal is enabled for the first time as a start time for measurement of a self-refresh period, and a first refresh period output unit for generating a first refresh period output signal that is enabled for a period from a time that the first period measurement start signal is enabled to a time that the first delayed oscillation signal is enabled for the first time.

Abstract: A burst mode control unit includes a burst period signal generation unit for generating a burst period signal which is enabled during a burst mode operation period, a burst pulse generation unit for generating a burst pulse, which is generated at every predetermined number of cycles during the enabled period of the burst period signal, in response to a read command and a write command, and a column access signal generation unit for receiving the burst signal and a clock signal and generating a column access signal which controls input and output of data during the burst mode operation period.

Abstract: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.

Abstract: A strobe signal controlling circuit is provided which includes an initial write controller configured to outputs a write pulse signal, which is activated in a write command, in synchronization with a clock signal, a DQS signal outputting unit configured to outputs a write DQS signal by synchronizing an output signal of the initial write controller to the clock signal, a control signal generator configured to generates a control signal in response to the output signal of the initial write controller, and a reset signal generator configured to responds to a reset signal and a DQS enable signal to output a reset signal to the DQS signal outputting module in synchronization with the control signal.

Abstract: A circuit for outputting data of a semiconductor memory apparatus is provided. A circuit for outputting data of a semiconductor memory apparatus according to an embodiment of the present invention includes a data clock generating unit that generates a data clock, a delayed clock generating unit that receives the data clock and outputs a delayed clock according to a change in an external voltage level, and a clock synchronizing unit that outputs data synchronized with the delayed clock as output data.

Abstract: A semiconductor IC in which a least significant bit of an external address signal is fixed to a signal level, the semiconductor integrated circuit includes an address control circuit configured to produce a carry signal, when a test mode signal is activated, in response to a column command signal and output an address signal, which is sequentially increased from an initial internal address signal, by latching the external address signal as the initial internal address signal and combining the latched initial internal address signal and the carry signal.

Abstract: There is provided a temperature detecting apparatus for improving operational characteristics, which vary according to the temperature, of elements in a semiconductor memory device. The temperature detecting apparatus of the present invention includes: a first oscillator that outputs a first oscillating signal in response to a first oscillator reset signal, the first oscillating signal being independent of the temperature; a second oscillator that outputs a second oscillating signal in response to a second oscillator enable signal, the second oscillating signal being dependent on the temperature; a comparator that compares an output pulse of the first oscillator with an output pulse of the second oscillator and then outputs a temperature detection comparison signal; and an output unit that outputs a temperature detection signal in response to an input of the temperature detection comparison signals.

Abstract: A self-refresh period measurement circuit of a semiconductor device is disclosed, herein which includes a period measurement start signal generator configured to receive a self-refresh signal and an oscillation signal, to allow a self-refresh operation to be performed, and generate a period measurement start signal, to set the time that the oscillation signal is enabled, and a refresh period output unit configured to receive the period measurement start signal and the oscillation signal, and generate a refresh period output signal that is enabled for a period from the time that the period measurement start signal is enabled to a time that the oscillation signal is enabled.

Abstract: A self-refresh period measurement circuit of a semiconductor device is disclosed, herein which includes a delay means for delaying the received oscillation signal by a unit self-refresh period to output a first delayed oscillation signal, and delaying the received oscillation signal to output a third delayed oscillation signal, a first period measurement start signal generator for generating a first period measurement start signal for setting a time that the oscillation signal is enabled for the first time as a start time for measurement of a self-refresh period, and a first refresh period output unit for generating a first refresh period output signal that is enabled for a period from a time that the first period measurement start signal is enabled to a time that the first delayed oscillation signal is enabled for the first time.

Abstract: A strobe signal controlling circuit is provided which includes an initial write controller configured to outputs a write pulse signal, which is activated in a write command, in synchronization with a clock signal, a DQS signal outputting unit configured to outputs a write DQS signal by synchronizing an output signal of the initial write controller to the clock signal, a control signal generator configured to generates a control signal in response to the output signal of the initial write controller, and a reset signal generator configured to responds to a reset signal and a DQS enable signal to output a reset signal to the DQS signal outputting module in synchronization with the control signal.

Abstract: An apparatus for detecting a refresh period of a semiconductor memory includes a signal generating unit that generates a plurality of signal pairs, each of which includes one among a plurality of first reference signals that are respectively generated with the same timing as first to (N?1)-th pulses of a refresh period signal of order N, and one among a plurality of second reference signals that correspond to the plurality of first reference signals and are respectively generated with the same timing as second to N-th pulses of the refresh period signal. A refresh period detecting unit detects the period of the refresh period signal using one among the plurality of signal pairs.

Abstract: The present invention provides a self-refresh period adaptable for testing cells that are weak against hot temperature stress. An apparatus for controlling a self-refresh operation in a semiconductor memory device includes a first period selector for generating one of a period-fixed pulse signal having a constant period and a period-variable pulse signal having a variable period based on a temperature of the semiconductor memory device in a test mode; and a self-refresh block for performing the self-refresh operation in response to an output of the first period selector.

Abstract: A self-refresh period measurement circuit of a semiconductor device is disclosed, herein which includes a shift register configured to receive an oscillation signal that is periodically enabled after a self-refresh signal is enabled, to allow a self-refresh operation to be performed, and delay the received oscillation signal by a unit self-refresh period to output a delayed oscillation signal, a period measurement start signal generator configured to receive the self-refresh signal and the oscillation signal and generate a period measurement start signal for setting a time that the oscillation signal is enabled for the first time as a start time for measurement of a self-refresh period, and a refresh period output unit configured to receive the period measurement start signal and the delayed oscillation signal from the shift register and generate a refresh period output signal that is enabled for a period from a time that the period measurement start signal is enabled to a time that the delayed oscillation si

Abstract: A precharge control circuit includes a precharge control unit and a precharge unit. The precharge control unit controls and outputs a precharge signal in response to a read command signal, a write command signal, and a first signal. The precharge unit precharges local input/output lines in response to a signal output from the precharge control unit.

Abstract: A circuit for outputting data of a semiconductor memory apparatus is provided. A circuit for outputting data of a semiconductor memory apparatus according to an embodiment of the present invention includes a data clock generating unit that generates a data clock, a delayed clock generating unit that receives the data clock and outputs a delayed clock according to a change in an external voltage level, and a clock synchronizing unit that outputs data synchronized with the delayed clock as output data.

Abstract: The present invention provides a self-refresh period adaptable for testing cells that are weak against hot temperature stress. An apparatus for controlling a self-refresh operation in a semiconductor memory device includes a first period selector for generating one of a period-fixed pulse signal having a constant period and a period-variable pulse signal having a variable period based on a temperature of the semiconductor memory device in a test mode; and a self-refresh block for performing the self-refresh operation in response to an output of the first period selector.

Abstract: The present invention provides a self-refresh period adaptable for testing cells that are weak against hot temperature stress. An apparatus for controlling a self-refresh operation in a semiconductor memory device includes a first period selector for generating one of a period-fixed pulse signal having a constant period and a period-variable pulse signal having a variable period based on a temperature of the semiconductor memory device in a test mode; and a self-refresh block for performing the self-refresh operation in response to an output of the first period selector.

Abstract: An apparatus for detecting a refresh period of a semiconductor memory includes a signal generating unit that generates a plurality of signal pairs, each of which includes one among a plurality of first reference signals that are respectively generated with the same timing as first to (N?1)-th pulses of a refresh period signal of order N, and one among a plurality of second reference signals that correspond to the plurality of first reference signals and are respectively generated with the same timing as second to N-th pulses of the refresh period signal. A refresh period detecting unit detects the period of the refresh period signal using one among the plurality of signal pairs.

Abstract: There is provided a temperature detecting apparatus for improving operational characteristics, which vary according to the temperature, of elements in a semiconductor memory device. The temperature detecting apparatus of the present invention includes: a first oscillator that outputs a first oscillating signal in response to a first oscillator reset signal, the first oscillating signal being independent of the temperature; a second oscillator that outputs a second oscillating signal in response to a second oscillator enable signal, the second oscillating signal being dependent on the temperature; a comparator that compares an output pulse of the first oscillator with an output pulse of the second oscillator and then outputs a temperature detection comparison signal; and an output unit that outputs a temperature detection signal in response to an input of the temperature detection comparison signals.