Abstract: A process for preparing a molten silicon melt from polycrystalline silicon for use in producing single crystal silicon by the Czochralski method is disclosed. Granular and chunk polycrystalline silicon are loaded into a Czochralski crucible as a mixed charge. Preferably, the granular polycrystalline silicon is loaded onto the bottom, mounded toward the centerline of the crucible, and not contacting the upper portion of the wall of the crucible. The chunk polycrystalline silicon is loaded onto the granular polycrystalline silicon. The granular polycrystalline silicon and chunk polycrystalline silicon are melted to form a silicon melt, preferably by heating the polycrystalline silicon from the bottom up such that a substantial portion of the granular polycrystalline silicon is melted before a substantial portion of the chunk polycrystalline silicon is melted.

Abstract: A Czochralski method of producing a single crystal silicon ingot having a uniform thermal history from a silicon melt contained in a crucible coaxial with the ingot. In the process the pulling rate of the end-cone of the ingot is maintained at a relatively constant rate which is comparable to the pulling rate for the second half of the main body of the ingot. During the pulling of the end-cone of the crystal at a constant rate, the process may be further refined by, either independently or in combination, increasing the heat supplied to the melt, reducing the crystal rotation rate and/or reducing the crucible rotation rate. The second half of the main body of a single crystal silicon ingot grown in accordance with this process exhibits a relatively uniform axial concentration of flow pattern defects and amount of oxygen precipitated.

Abstract: A Czochralski method for producing monocrystals wherein a single crystal silicon rod is pulled from a silicon melt contained in a crucible within a chamber. After pulling the single crystal silicon rod from a silicon melt in a chamber, the chamber is cooled by flowing a gas having a thermal conductivity of at least about 55.times.10.sup.-5 g.cal./(sec..multidot.cm.sup.2)(.degree.C./cm) at 800.degree. K into the chamber. The preferred cooling gas is a helium-containing gas.

Abstract: A silicon single crystal prepared by the Czochralski method including a neck having an upper portion, an intermediate portion, and a lower portion. The upper portion contains dislocations. The intermediate portion is between the upper and lower portions. A majority of the intermediate and lower portions has a diameter greater than 10 millimeters, and the lower portion is free of dislocations. The crystal also includes an outwardly flaring segment adjacent the lower portion of the neck, and a body adjacent the outwardly flaring segment.

Abstract: A silicon single crystal prepared by the Czochralski method including a neck having an upper portion, an intermediate portion, and a lower portion. The upper portion contains dislocations. The intermediate portion is between the upper and lower portions. A majority of the intermediate and lower portions has a diameter greater than 10 millimeters, and the lower portion is free of dislocations. The crystal also includes an outwardly flaring segment adjacent the lower portion of the neck, and a body adjacent the outwardly flaring segment.

Abstract: A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer is then bound to an oxide layer on the surface of a separate wafer to form a bonded silicon-on-oxide structure. The entire assembly is, in effect inverted, and what had been the lower surface of the bulk silicon wafer, is removed to the bottom of the deepest trench step. In this bonded SOI structure, regions between the trenches are deep and suitable for bipolar device fabrication, while the trench steps form shallow regions suitable for fabrication of CMOS devices.

Abstract: A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer is then bound to an oxide layer on the surface of a separate wafer to form a bonded silicon-on-oxide structure. The entire assembly is, in effect inverted, and what had been the lower surface of the bulk silicon wafer, is removed to the bottom of the deepest trench step. In this bonded SOI structure, regions between the trenches are deep and suitable for bipolar device fabrication, while the trench steps form shallow regions suitable for fabrication of CMOS devices.

Abstract: A vertical bipolar transistor is constructed with reduced step height by codeposition of a polysilicon base contact member and an epitaxial device layer, thereby placing the base contact below the device surface, and by the use of a doped glass layer as a dopant source for the base contact and as a dopant source to provide a continuous conductive path to the base, and as the dielectric separating the base contact from the emitter contact, and as an etch stop when forming the base implantation aperture.

Abstract: A multiprobe apparatus for probing a device having a plurality of contacts includes a holder for holding the device in a fixed position; a plurality of electrically conducting elongated probes, each probe being adapted for electrical communication with a respective one of the contacts by tangential linear contact along the length of the probe; and a probe support for supporting the probes and for maintaining the probes in electrical communication with the contacts.

Abstract: A vertical bipolar transistor is constructed with reduced step height by codeposition of a polysilicon base contact member and an epitaxial device layer, thereby placing the base contact below the device surface, and by the use of a doped glass layer as a dopant source for the base contact and as a dopant source to provide a continuous conductive path to the base, and as the dielectric separating the base contact from the emitter contact, and as an etch stop when forming the base implantation aperture.

Abstract: An inexpensive and reliable technique for forming connections to a substrate or buried layer of a semiconductor structure employs a laser to melt a small, selected region of a lightly doped layer and a highly doped underlying layer. Extremely rapid diffusion of impurities and mixing of materials within the liquid phase of the melt quickly creates a uniformly doped conductive region when the melt is allowed to recrystallize.

Abstract: A semiconductor structure including a doped semiconductor substrate defining a surface. A buffer layer of epitaxial semiconductor material overlies the substrate surface, the buffer layer having a relatively higher dopant concentration than the substrate and being virtually free from oxygen precipitation. A layer of intrinsic semiconductor material overlies the buffer layer, and a device layer of epitaxial semiconductor material is situated on the intrinsic layer. The device layer is formed to have a relatively lower dopant concentration than the first layer. Isolation regions extend from a surface of the device layer into the buffer layer for forming an electrically isolated device region in the device layer. At least one active device is formed in the isolated device region.

Abstract: A semiconductor structure including a doped semiconductor substrate defining a surface. A buffer layer of epitaxial semiconductor material overlies the substrate surface, the buffer layer having a relatively higher dopant concentration than the substrate and being virtually free from oxygen precipitation. A layer of intrinsic semiconductor material overlies the buffer layer, and a device layer of epitaxial semiconductor material is situated on the intrinsic layer. The device layer is formed to have a relatively lower dopant concentration than the first layer. Isolation regions extend from a surface of the device layer into the buffer layer for forming an electrically isolated device region in the device layer. At least one active device is formed in the isolated device region.

Abstract: An improvement in the method and apparatus for growing a semiconductor crystal by the Czochralski technique comprising the steps of applying a rotating transverse magnetic field to molten semiconductor material held in a crucible during the seed crystal pulling and crystal formation step, to cause the molten material to rotate within the crucible, and simultaneously increasing the rotational velocity of the magnetic field during this crystal formation as a function of the length of the crystal pulled from said molten material to thereby vary the rotation rate of the molten material. These steps result in the uniform axial distribution of oxygen in the crystal.

Abstract: In combination with a susceptor particularly suited for use in growing a ribbon crystal employing edge-defined film-fed growth techniques and characterized by a susceptor including a die through which a melt is drawn for forming a crystal ribbon, a pair of jets for directing a stream of fluid coolant along a path extended to impinge on the susceptor in close proximity with the die in non-incident relation with the crystal being grown.

Abstract: Apparatus for pulling a ribbon shaped crystal from a melt of the same downwardly through a shaping guide having a "V" shaped longitudinal trough for containing the melt. The inner wall of the trough is a die set having a longitudinal slit at the apex of the "V".

Abstract: Mechanical components such as dies and crucibles, which come in contact with a silicon melt during the formation of single crystalline shaped silicon particles, e.g. thin sheets or ribbons, are coated with silicon oxynitride deposited by chemical vapor deposition techniques.

Abstract: Mechanical components, e.g. die and/or crucible or the like structures with which single silicon crystals are grown from the melt as shaped articles in thin sheet or ribbon geometry, are advantageously comprised, for their material of construction, of a suitable thermally stable and inert foundation substrate coated or provided on at least the silicon-contacting surface(s) thereof with a thin, uniform, integral surface layer deposit of pyrolitic silicon nitride (Si.sub.3 N.sub.4) obtained by the chemical vapor deposition (i.e., "CVD") technique.