Abstract: An integrated exhaust gas recirculation (EGR) valve housing includes: a temperature control passage configured to include a first cooling channel which connects a water jacket formed in an engine to a radiator and a second cooling channel which is branched from the first cooling channel and extends to an EGR cooler cooling re-circulated exhaust gas; and an auxiliary cooling passage configured to guide cooling water introduced into the second cooling channel to the EGR valve housing, whereby it is possible to easily dispose the EGR valve housing in the engine compartment by integrating the parts through which the cooling water is discharged from the engine with the cooling water channel connected to the EGR valve housing.

Abstract: A method for diagnosing an electric water pump of an internal combustion engine includes determining whether a present condition is a coil-open diagnosis condition that enables diagnosis of whether any coil of a sensorless 3-phase motor used in the electric water pump is open. When the coil-open diagnosis condition is satisfied, whether a coil of one phase is open is determined by using a change in phase currents. When the coil-open diagnosis condition is satisfied, whether coils of two phases are open is determined by using a magnitude of a motor torque or a magnitude of an average phase current. When the coil-open diagnosis condition is satisfied, whether any coil of the motor is open during driving of the motor is determined by using a variation in the motor torque.

Abstract: A method for diagnosing an electronic water pump of an engine in a vehicle includes determining whether a stall occurs while a sensorless 3-phase motor used for the electronic water pump of the engine is driven, based on a peak value of a torque of the motor. The method further includes determining whether the stall occurs while the motor is stopped, based on the torque of the motor.

Abstract: A method for diagnosing an electric water pump of an internal combustion engine includes determining whether a present condition is a coil-open diagnosis condition that enables diagnosis of whether any coil of a sensorless 3-phase motor used in the electric water pump is open. When the coil-open diagnosis condition is satisfied, whether a coil of one phase is open is determined by using a change in phase currents. When the coil-open diagnosis condition is satisfied, whether coils of two phases are open is determined by using a magnitude of a motor torque or a magnitude of an average phase current. When the coil-open diagnosis condition is satisfied, whether any coil of the motor is open during driving of the motor is determined by using a variation in the motor torque.

Abstract: An integrated exhaust gas recirculation (EGR) valve housing includes: a temperature control passage configured to include a first cooling channel which connects a water jacket formed in an engine to a radiator and a second cooling channel which is branched from the first cooling channel and extends to an EGR cooler cooling re-circulated exhaust gas; and an auxiliary cooling passage configured to guide cooling water introduced into the second cooling channel to the EGR valve housing, whereby it is possible to easily dispose the EGR valve housing in the engine compartment by integrating the parts through which the cooling water is discharged from the engine with the cooling water channel connected to the EGR valve housing.

Abstract: The inventive concept provides porous, low-k dielectric materials and methods of manufacturing and using the same. In some embodiments, porous, low-k dielectric materials are manufactured by forming a porogen-containing dielectric layer on a substrate and then removing at least a portion of said porogen from the layer.

Abstract: A semiconductor device can include wiring lines on a substrate and an interlayer insulating structure, between ones of the wiring lines. The wiring lines can include a pore-containing layer that includes a plurality of pores extending away from a surface of the substrate, wherein ones of the pores have respective volumes that increase with a distance from the substrate until reaching an air gap layer above the pore-containing layer and beneath uppermost surfaces of the wiring lines.

Abstract: A method of forming through silicon vias (TSVs) uses a low-k dielectric material as a via insulating layer to thereby improve step coverage and minimize resistive capacitive (RC) delay. To this end, the method includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.

Abstract: A semiconductor device can include wiring lines on a substrate and an interlayer insulating structure, between ones of the wiring lines. The wiring lines can include a pore-containing layer that includes a plurality of pores extending away from a surface of the substrate, wherein ones of the pores have respective volumes that increase with a distance from the substrate until reaching an air gap layer above the pore-containing layer and beneath uppermost surfaces of the wiring lines.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a via hole comprised of a first region having a first width and a second region having a second width greater than the first width, wherein at least a portion of the substrate is exposed in the via hole, and an insulating region having an air gap spaced apart from and surrounding the first region of the via hole.

Abstract: A semiconductor device comprises a top surface having a first contact, a bottom surface having a second contact, a via hole penetrating a substrate, an insulation layer structure on a sidewall of the via hole, the insulation layer structure having an air gap therein, a through electrode having an upper surface and a lower surface on the insulation layer structure, the through electrode filling the via hole and the lower surface being the second contact, and a metal wiring electrically connected to the upper surface of the through electrode and electrically connected to the first contact.

Abstract: A method of forming through silicon vias (TSVs) uses a low-k dielectric material as a via insulating layer to thereby improve step coverage and minimize resistive capacitive (RC) delay. To this end, the method includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.

Abstract: Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.

Abstract: Disclosed herein are novel compounds of Formula (1) as defined in the specification having excellent inhibitory activity against dipeptidyl peptidase-IV (DPP-IV), methods of preparing the same and pharmaceutical compositions comprising the same as an active agent.

Abstract: A method of forming through silicon vias (TSVs) includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.

Abstract: Disclosed are new compounds of formula (1) exhibiting excellent activity for glucokinase, pharmaceutical compositions having the same as an active ingredient, and a method of using the same as an active ingredient for lowering blood glucose level: in which the substituents are as defined herein.

Abstract: The inventive concept provides porous, low-k dielectric materials and methods of manufacturing and using the same. In some embodiments, porous, low-k dielectric materials are manufactured by forming a porogen-containing dielectric layer on a substrate and then removing at least a portion of said porogen from the layer.

Abstract: A semiconductor device comprises a top surface having a first contact, a bottom surface having a second contact, a via hole penetrating a substrate, an insulation layer structure on a sidewall of the via hole, the insulation layer structure having an air gap therein, a through electrode having an upper surface and a lower surface on the insulation layer structure, the through electrode filling the via hole and the lower surface being the second contact, and a metal wiring electrically connected to the upper surface of the through electrode and electrically connected to the first contact.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a via hole comprised of a first region having a first width and a second region having a second width greater than the first width, wherein at least a portion of the substrate is exposed in the via hole, and an insulating region having an air gap spaced apart from and surrounding the first region of the via hole.

Abstract: A method of forming through silicon vias (TSVs) includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.