Abstract: A semiconductor memory device may include a clock buffer, a command decoder and a write recovery time control circuit. The clock buffer may generate an internal clock signal based on an external clock signal. The command decoder may generate a write command signal by decoding an external command signal. The write recovery time control circuit may gate a plurality of bank pre-charge control signals in a wave pipeline mode based on the internal clock signal, the write command signal and a write recovery time control signal having a plurality of bits to generate a plurality of gated bank pre-charge control signals. Therefore, the semiconductor memory device may decrease a number of flip-flops required to control a write recovery time.

Abstract: A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information.

Abstract: A circuit and method are provided for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device, the circuit including a local input/output line, a local from/to global input/output multiplexer in signal communication with the local input/output line, a global input/output line in signal communication with the local from/to global input/output multiplexer, and a local from/to global input/output controller having an input node and an output node, the input node disposed for receiving a signal indicative of an input or output operation, and the output node in signal communication with a gate of the local from/to global input/output multiplexer for providing a gate signal of a first or second level in the presence of the output operation, and a gate signal of a third level in the presence of the input operation.

Abstract: Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time.

Abstract: A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information.

Abstract: An input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof are provided. The example semiconductor memory device may include a clock buffer configured to generate an internal clock signal based on an external clock signal, a command decoder configured to decode an external command signal to generate a write command signal and an input latency control circuit configured to gate an address signal in a pipeline mode to generate a column address signal and a bank address signal based on the internal clock signal, the write command signal and the write latency signal.

Abstract: An oven, which both satisfies heat insulating and cooling of a door by adjusting an air flow in channels formed in the door. The oven includes a plurality of channels provided in a door, into which external air flows, accompanied with air discharged by a discharge duct, such that the air flows in the plurality of the channels, and a flow conversion part formed above at least one of the plurality of the channels for stagnating the flow of air. Since the door insulates a cooking chamber from heat and is cooled using a difference of pressures between upper and lower portions of the door, the oven concurrently satisfies conflicting two requirements, such as heat insulating and cooling of the door.

Abstract: A method for testing a memory cell array of a semiconductor memory device in a parallel bit test mode includes selecting first data from one of a plurality of memory regions in the memory array for output from the memory device via an input/output pad, and then selecting second data from another of the plurality of memory regions for output via the input/output pad. The first and second data can be selected from memory regions sharing a row select or a column select control line. Alternatively, one of the first and second data can be selected from memory regions sharing a row select control line, and the other can be selected from memory regions sharing a column select control line. Therefore, a parallel bit test can be performed using fewer input/output pads, and a larger number of semiconductor memory devices can simultaneously be tested. Related circuits are also discussed.

Abstract: A capacitor comprising an electrode made from an electroconductive material and activated carbon in combination with quaternary ammonium tosylate, and a method for manufacturing the same. The method enables the preparation of a high capacitance electrode without special facilities. The capacitor exhibits high specific capacitance and a high energy density.

Abstract: Disclosed is a methane engine for rocket propulsion. A methane supply pump (36) operated by a turbine (30) supplies a part of methane to a nozzle cooling channel (56, 156) installed on a nozzle (54, 154) of a combustor (50, 150) and supplies the other part of the methane to a combustion chamber cooling channel (53, 153) installed on a combustion chamber (52, 152) of the combustor (50, 150) so as to regulate the amount of methane supplied to a mixing head (51, 151) while maintaining the cooling properties of the combustor (50, 150), thus providing extensity of coping with changes in propulsive force and design of the combustor (50, 150). Further, a part of methane in a gas state discharged from the combustion chamber cooling channel (53, 153) is supplied to a mixing head (76) of a gas generator (94), thus providing the re-liability of the engine.

Abstract: A folding and interpolating analog,-to-digital converter (ADC) includes a preamp unit, a first folding stage, a second folding stage, a comparison unit and an encoder. The preamp unit receives an analog input signal and reference voltages to generate reference signals. The first folding stage generates a first group of folding signals based on the reference signals. The second folding stage generates a second group of folding signals based the first group. The comparison unit generates a digital code based on the folding signals in the second group. The encoder encodes the digital code. Therefore, the ADC can increase a resolution and a conversion speed, but reduce interpolating errors.

Abstract: An output circuit of a semiconductor memory device includes a first data path, a second data path and a third data path. The first data path transfers a sense output signal, and latches the sense output signal to output the sense output signal to a first node. The second data path transfers the sense output signal, and latches the sense output signal to output the sense output signal to the first node. The third data path latches a signal of the first node, and transfers the signal of the first node to generate output data. Accordingly, the semiconductor memory device including the output circuit can operate at a relatively higher frequency using a pseudo-pipeline structured circuit, which combines a wave pipeline structure with a full pipeline structure.

Abstract: An apparatus for aligning input data in a semiconductor device includes at least one alignment block and a decision block. The at least one alignment block is for aligning serial input data into groups of parallel data synchronized to at least one divided data strobe signal for increasing margin between the maximum and minimum tDQSS values. The decision block is for selecting one of the groups of parallel data as valid data in response to synchronization information generated for removing any invalid data in the serial input data resulting from a write gap.

Abstract: A semiconductor memory device may include a clock buffer, a command decoder and a write recovery time control circuit. The clock buffer may generate an internal clock signal based on an external clock signal. The command decoder may generate a write command signal by decoding an external command signal. The write recovery time control circuit may gate a plurality of bank pre-charge control signals in a wave pipeline mode based on the internal clock signal, the write command signal and a write recovery time control signal having a plurality of bits to generate a plurality of gated bank pre-charge control signals. Therefore, the semiconductor memory device may decrease a number of flip-flops required to control a write recovery time.

Abstract: A door damper. The door damper includes a rotational shaft rotatably coupled to a door, a rotating resistance unit to generate rotating resistance to the rotational shaft, and a latching device latched to the rotational shaft and the door so as to allow the door and the rotational shaft to rotate together in a predetermined region. The latching device includes a free rotating section enabling free rotation of the door at an initial stage of opening the door, and a latching section enabling the latching device to be latched to the rotational shaft and the door at a final stage of opening the door so as to allow the door and the rotational shaft to rotate together. With the door damper, the door of electronic appliances can be smoothly opened without impact, and can be easily closed.

Abstract: A heat radiating apparatus is provided which includes a heat sink configured to be positioned in thermal contact with a heat source in order to take heat from the heat source, at least one heat pipe having a portion connected to the heat sink and configured to transfer the heat from the heat sink, a heat exchanger in thermal communication with the at least one heat pipe, formed with a through chamber at a center thereof, and positioned adjacent to the heat sink, and a fan unit installed at least partially in the through chamber of the heat exchanger and configured to generate an airflow through the heat exchanger. Heat generated not only by a specified heat source but also by an interior of electronic equipment can be quickly radiated.

Abstract: A semiconductor device includes an upper gate trench crossing an active region of a semiconductor substrate, a lower gate trench overlapping the upper gate trench at both ends, disposed at a lower level than the upper gate trench, and having a smaller width than the upper gate trench and wherein the lower gate trench is spaced apart from sidewalls of the upper gate trench. The semiconductor device further includes a gate pattern partially covering the bottom of the upper gate trench between the sidewall of the upper gate trench and the lower gate trench, filling the lower gate trench, and covering sidewalls of the active region adjacent to the bottom and sidewalls of the lower gate trench.

Abstract: A circuit and method are provided for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device, the circuit including a local input/output line, a local from/to global input/output multiplexer in signal communication with the local input/output line, a global input/output line in signal communication with the local from/to global input/output multiplexer, and a local from/to global input/output controller having an input node and an output node, the input node disposed for receiving a signal indicative of an input or output operation, and the output node in signal communication with a gate of the local from/to global input/output multiplexer for providing a gate signal of a first or second level in the presence of the output operation, and a gate signal of a third level in the presence of the input operation.

Abstract: There is provided a nozzle apparatus for stripping an edge bead from a wafer, which includes a rotatable support arm, and a side rinse nozzle coupled to a leading end of the support arm to remove the bead of photoresist remaining on the edge of a wafer. The side rinse nozzle has a first nozzle for removing the bead on the upper surface of the wafer edge, and a second nozzle for removing the bead on the outer end surface of the wafer. The first and second nozzles each have a shape such that a length thereof is long in a radial direction of the wafer and a width thereof is narrow.

Abstract: In an apparatus for performing an edge exposure process on an edge portion of a photoresist film that is formed on a semiconductor wafer, light provided from a light source is formed to have a ring shape corresponding to a shape of an edge portion of the wafer by an optical unit. The ring-shaped light is irradiated onto the edge portion of the wafer through a ring lens. Thus, the light efficiency is improved. Further, since there is no need to rotate the wafer, a side surface profile of the photoresist film is improved.