Abstract: A semiconductor system includes a controller configured to output a command address, data, and a write clock and an inverted write clock for latching the data through a channel, configured to output the write clock and the inverted write clock having a first set level and a second set level, respectively, by incorporating information with regard to characteristics of the channel during a pre-level interval, and configured to output the write clock and the inverted write clock that periodically toggle during a toggle interval, and a semiconductor device configured to latch and store the data in synchronization with the write clock and the inverted write clock.

Abstract: Disclosed are a method and apparatus for reusing wastewater. The method for reusing wastewater disclosed herein includes: generating a mixed wastewater by mixing multiple types of wastewater (S20); performing a first purification by passing the mixed wastewater through a flocculation-sedimentation unit (S40); performing a second purification by passing an effluent of the flocculation-sedimentation unit through a membrane bioreactor (MBR) (S60); performing a third purification by passing an effluent of the MBR through a reverse-osmosis membrane unit (S80); and reusing an effluent of the reverse-osmosis membrane unit as cooling water or industrial water (S100).

Abstract: A semiconductor device includes a command pulse generation circuit configured to generate a first command pulse in synchronization with a frequency division clock and to generate a second command pulse in synchronization with an inverted frequency division clock, based on a test write command. The semiconductor device also includes an alignment data generation circuit configured to align first internal data in an in-phase manner to generate first alignment data, based on the first command pulse, and to align second internal data in an out-of-phase manner to generate second alignment data, based on the second command pulse. The semiconductor device further includes a phase detection circuit configured to determine synchronization states of a clock and the frequency division clock, based on the first alignment data and the second alignment data.

Abstract: An amplifier circuit includes a first input unit, a second input unit, a first current supply unit, and a second current supply unit. The first input unit changes a voltage level of a first output node based on a first input signal. The second input unit changes a voltage level of a second output node based on a second input signal. The first current supply unit supplies a first current to the first output node based on a voltage level of the first output node and boosts the voltage level of the first output node for a predetermined time when the voltage level of the first output node is changed. The second current supply unit supplies a second current to the second output node based on the voltage level of the first output node.

Abstract: A semiconductor system includes a controller configured to transmit a command address and a plurality of read strobe signals, and a semiconductor device including a first rank and a second rank that are configured to receive the command address and the plurality of read strobe signals and to perform a write operation and a read operation based on the command address. In the semiconductor device, the first rank is configured to calibrate a termination resistance value of the first rank to a target resistance value when a write operation for the first rank is performed. In the semiconductor device, the first rank is configured to calibrate the termination resistance value of the first rank to a dynamic resistance value based on the plurality of read strobe signals when a write operation for the second rank is performed.

Abstract: A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

Abstract: A memory system includes a memory controller and a memory device. The memory controller accesses the memory device by providing a system clock signal, a data clock signal, and a chip selection signal and provides a data clock enable signal to the memory device after the access to the memory device. The memory device communicates with the memory controller based on the system clock signal, the data clock signal, and the data clock enable signal.

Abstract: A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

Abstract: A duobinary receiver includes a signal dividing circuit configured to output a plurality of data by dividing an input signal according to a plurality of multi-phase sampling clocks signals; a level detecting circuit configured to output a plurality of state signals respectively corresponding to duobinary levels of the plurality of data; and a data converting circuit configured to decode the plurality of state signals to output a corresponding plurality of bits.

Abstract: A transceiver includes a duobinary conversion circuit configured to determine a level of an input signal which is a duobinary signal according to an intermediate voltage, a first reference voltage higher than the intermediate voltage, and a second reference voltage lower than the intermediate voltage, and to convert the input signal into a non-return-to-zero (NRZ) signal; and a control circuit configured to generate one or more control signals to substantially remove inter-symbol interference (ISI) between symbols of the input signal, and to adjust the first reference voltage, or the second reference voltage, or both according to the level of the input signal.

Abstract: A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

Abstract: A clock compensation circuit includes a delay circuit configured to generate a plurality of second clock signals by delaying a plurality of first clock signals, a voltage conversion circuit configured to convert phase differences between the plurality of second clock signals into voltages and output converted voltages as a plurality of phase difference voltages, and a comparison circuit configured to generate a plurality of phase difference detection signals by comparing the plurality of phase difference voltages with a reference voltage. The clock compensation circuit also includes a phase error control circuit configured to generate a plurality of control signals for controlling the delay circuit, the voltage conversion circuit, and the comparison circuit according to any of the plurality of second clock signals and the plurality of phase difference detection signals.

Abstract: A clock distribution circuit may include a data clock generation circuit configured to be input a power source voltage and configured to generate an internal clock signal according to an external clock signal; and a global distribution circuit includes a first circuit and a second circuit coupled to a global line, configured to be input a power source voltage and configured to receive the internal clock signal through the first circuit and distribute the internal clock signal to an exterior of the clock distribution circuit through the second circuit, wherein a first bias voltage provided to the first circuit and a second bias voltage provided to the second circuit are controlled independently of each other.

Abstract: A transmitter provides a duobinary signal corresponding to one of level 0, level 1, and level 2 based on first data and second data, and includes a pull-up driving circuit including a plurality of pull-up resistors selectively coupled between a first power source and a transmission node according to the first data and the second data; and a pull-down driving circuit including a plurality of pull-down resistors selectively coupled between the transmission node and a second power source, wherein at least one of the plurality of pull-up resistors is coupled between the first power source and the transmission node both when the first data is activated and when the second data is activated, or at least one of the plurality of pull-down resistors is coupled between the second power source and the transmission node both when the first data is activated and when the second data is activated.

Abstract: A duobinary receiver includes a signal dividing circuit configured to output a plurality of data by dividing an input signal according to a plurality of multi-phase sampling clocks signals; a level detecting circuit configured to output a plurality of state signals respectively corresponding to duobinary levels of the plurality of data; and a data converting circuit configured to decode the plurality of state signals to output a corresponding plurality of bits.

Abstract: A clock compensation circuit includes a delay circuit configured to generate a plurality of second clock signals by delaying a plurality of first clock signals, a voltage conversion circuit configured to convert phase differences between the plurality of second clock signals into voltages and output converted voltages as a plurality of phase difference voltages, and a comparison circuit configured to generate a plurality of phase difference detection signals by comparing the plurality of phase difference voltages with a reference voltage. The clock compensation circuit also includes a phase error control circuit configured to generate a plurality of control signals for controlling the delay circuit, the voltage conversion circuit, and the comparison circuit according to any of the plurality of second clock signals and the plurality of phase difference detection signals.

Abstract: A transceiver includes a duobinary conversion circuit configured to determine a level of an input signal which is a duobinary signal according to an intermediate voltage, a first reference voltage higher than the intermediate voltage, and a second reference voltage lower than the intermediate voltage, and to convert the input signal into a non-return-to-zero (NRZ) signal; and a control circuit configured to generate one or more control signals to substantially remove inter-symbol interference (ISI) between symbols of the input signal, and to adjust the first reference voltage, or the second reference voltage, or both according to the level of the input signal.

Abstract: A clock compensation circuit includes a delay circuit configured to generate a plurality of second clock signals by delaying a plurality of first clock signals, a voltage conversion circuit configured to convert phase differences between the plurality of second clock signals into voltages and output converted voltages as a plurality of phase difference voltages, and a comparison circuit configured to generate a plurality of phase difference detection signals by comparing the plurality of phase difference voltages with a reference voltage. The clock compensation circuit also includes a phase error control circuit configured to generate a plurality of control signals for controlling the delay circuit, the voltage conversion circuit, and the comparison circuit according to any of the plurality of second clock signals and the plurality of phase difference detection signals.

Abstract: An amplifier circuit includes a first input unit, a second input unit, a first current supply unit, and a second current supply unit. The first input unit changes a voltage level of a first output node based on a first input signal. The second input unit changes a voltage level of a second output node based on a second input signal. The first current supply unit supplies a first current to the first output node based on a voltage level of the first output node and boosts the voltage level of the first output node for a predetermined time when the voltage level of the first output node is changed. The second current supply unit supplies a second current to the second output node based on the voltage level of the first output node.

Abstract: An amplifier circuit includes a first input unit, a second input unit, a first current supply unit, and a second current supply unit. The first input unit changes a voltage level of a first output node based on a first input signal. The second input unit changes a voltage level of a second output node based on a second input signal. The first current supply unit supplies a first current to the first output node based on a voltage level of the first output node and boosts the voltage level of the first output node for a predetermined time when the voltage level of the first output node is changed. The second current supply unit supplies a second current to the second output node based on the voltage level of the first output node.