Abstract: A clock compensation circuit includes a delay circuit configured to generate a plurality of second clock signals by delaying a plurality of first clock signals, a voltage conversion circuit configured to convert phase differences between the plurality of second clock signals into voltages and output converted voltages as a plurality of phase difference voltages, and a comparison circuit configured to generate a plurality of phase difference detection signals by comparing the plurality of phase difference voltages with a reference voltage. The clock compensation circuit also includes a phase error control circuit configured to generate a plurality of control signals for controlling the delay circuit, the voltage conversion circuit, and the comparison circuit according to any of the plurality of second clock signals and the plurality of phase difference detection signals.

Abstract: An amplifier circuit includes a first input unit, a second input unit, a first current supply unit, and a second current supply unit. The first input unit changes a voltage level of a first output node based on a first input signal. The second input unit changes a voltage level of a second output node based on a second input signal. The first current supply unit supplies a first current to the first output node based on a voltage level of the first output node and boosts the voltage level of the first output node for a predetermined time when the voltage level of the first output node is changed. The second current supply unit supplies a second current to the second output node based on the voltage level of the first output node.

Abstract: An amplifier circuit includes a first input unit, a second input unit, a first current supply unit, and a second current supply unit. The first input unit changes a voltage level of a first output node based on a first input signal. The second input unit changes a voltage level of a second output node based on a second input signal. The first current supply unit supplies a first current to the first output node based on a voltage level of the first output node and boosts the voltage level of the first output node for a predetermined time when the voltage level of the first output node is changed. The second current supply unit supplies a second current to the second output node based on the voltage level of the first output node.

Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a first buffer configured to generate a first preliminary clock and a first preliminary clock bar based on an external clock, an external clock bar, and a node voltage code. The semiconductor apparatus may include a node voltage control circuit configured to generate the node voltage code based on a control code.

Abstract: A buffer circuit may include: an amplifying circuit configured to change, based on a first input signal and a second input signal, voltage levels of a first output node and a second output node in a range between a first power voltage and a second power voltage; a latch circuit configured to latch the voltage levels of the first output node and the second output node; a first variable load configured to adjust, based on a reset signal, an amount of current provided by a first power voltage terminal at the first power voltage to the first output node; a second variable load configured to adjust, based on the reset signal, an amount of current provided by the first power voltage terminal to the second output node; and a reset circuit configured to drive the first output node to the second power voltage based on the reset signal.

Abstract: A receiver includes an amplification circuit and a compensation circuit. The amplification circuit changes a voltage level of a first output node based on an input signal and changes a voltage level of a second output node based on a reference voltage. The compensation circuit changes the voltage level of the second output node based on the input signal and changes the voltage level of the first output node based on the reference voltage. The amplification circuit includes first type transistors configured to receive the input signal and the reference voltage. The compensation circuit includes second type transistors configured to receive the input signal and the reference voltage.

Abstract: A clock distribution circuit may include a data clock generation circuit configured to be input a power source voltage and configured to generate an internal clock signal according to an external clock signal; and a global distribution circuit includes a first circuit and a second circuit coupled to a global line, configured to be input a power source voltage and configured to receive the internal clock signal through the first circuit and distribute the internal clock signal to an exterior of the clock distribution circuit through the second circuit, wherein a first bias voltage provided to the first circuit and a second bias voltage provided to the second circuit are controlled independently of each other.

Abstract: A semiconductor device may include a first buffer, a second buffer, a divider circuit and an internal signal generation circuit. The first buffer may buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal. The second buffer may generate a second data strobe buffering signal based on the first input signal and a reference xvoltage. The divider circuit may divide the second data strobe buffering signal to generate a divided signal and a divided bar signal. The internal signal generation circuit may be configured to generate a first to fourth data latch timing signals having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided buffering signal.

Abstract: A buffering circuit includes a first signal input/output unit that generates an output bar signal in response to an input signal, a second signal input/output unit that generates an output signal in response to an input bar signal, and a connection unit that electrically connects and disconnects an output node of the first signal input/output unit and a current sink node of the second signal input/output unit to/from each other in response to a control signal, and electrically connects and disconnects a current sink node of the first signal input/output unit and an output node of the second signal input/output unit to/from each other in response to the control signal.

Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a first buffer configured to generate a first preliminary clock and a first preliminary clock bar based on an external clock, an external clock bar, and a node voltage code. The semiconductor apparatus may include a node voltage control circuit configured to generate the node voltage code based on a control code.

Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a first buffer configured to generate a first preliminary clock and a first preliminary clock bar based on an external clock, an external clock bar, and a node voltage code. The semiconductor apparatus may include a node voltage control circuit configured to generate the node voltage code based on a control code.

Abstract: A semiconductor device may include an amplification circuit. The amplification circuit may be configured to generate an output signal and an output bar signal based on a mode signal, first and second control signals, an input signal, and an input bar signal. The amplification circuit may determine voltage levels of the output signal and the output bar signal based on the mode signal and the first and second control signals regardless of the input signal and the input bar signal.

Abstract: A semiconductor device may include a first buffer, a second buffer, a divider circuit and an internal signal generation circuit. The first buffer may buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal. The second buffer may generate a second data strobe buffering signal based on the first input signal and a reference xvoltage. The divider circuit may divide the second data strobe buffering signal to generate a divided signal and a divided bar signal. The internal signal generation circuit may be configured to generate a first to fourth data latch timing signals having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided buffering signal.

Abstract: A semiconductor device may include an input control circuit, a counting circuit, an output control circuit, and a counting operation control circuit. The input control circuit may output a counting input signal based on an input signal and a counting over signal. The counting circuit may generate a preliminary counting code based on the counting input signal. The output control circuit may generate a counting code based on the preliminary counting code. The counting operation control circuit may generate the counting over signal based on a part of the counting code.

Abstract: A semiconductor device may include a first buffer, a second buffer, a divider circuit and an internal signal generation circuit. The first buffer may buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal. The second buffer may generate a second data strobe buffering signal based on the first input signal and a reference voltage. The divider circuit may divide the second data strobe buffering signal to generate a divided signal and a divided bar signal. The internal signal generation circuit may be configured to generate a first to fourth data latch timing signals having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided buffering signal.

Abstract: An amplifier circuit includes a first input unit, a second input unit, a first current supply unit, and a second current supply unit. The first input unit changes a voltage level of a first output node based on a first input signal. The second input unit changes a voltage level of a second output node based on a second input signal. The first current supply unit supplies a first current to the first output node based on a voltage level of the first output node and boosts the voltage level of the first output node for a predetermined time when the voltage level of the first output node is changed. The second current supply unit supplies a second current to the second output node based on the voltage level of the first output node.

Abstract: A semiconductor device may include a first buffer, a second buffer, a divider circuit and an internal signal generation circuit. The first buffer may buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal. The second buffer may generate a second data strobe buffering signal based on the first input signal and a reference voltage. The divider circuit may divide the second data strobe buffering signal to generate a divided signal and a divided bar signal. The internal signal generation circuit may be configured to generate a first to fourth data latch timing signals having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided buffering signal.

Abstract: A clock distribution circuit may include a data clock generation circuit configured to generate an internal clock signal using an external clock signal. The clock distribution circuit may be configured to receive the internal clock signal through a first circuit and distribute the internal clock signal to an exterior of the clock distribution circuit through a second circuit coupled to a global line. A first bias voltage provided to the first circuit and the data clock generation circuit and a second bias voltage provided to the second circuit may be controlled independently of each other.

Abstract: A buffering circuit includes a first signal input/output unit that generates an output bar signal in response to an input signal, a second signal input/output unit that generates an output signal in response to an input bar signal, and a connection unit that electrically connects and disconnects an output node of the first signal input/output unit and a current sink node of the second signal input/output unit to/from each other in response to a control signal, and electrically connects and disconnects a current sink node of the first signal input/output unit and an output node of the second signal input/output unit to/from each other in response to the control signal.

Abstract: A buffer circuit may include: an amplifying circuit configured to change, based on a first input signal and a second input signal, voltage levels of a first output node and a second output node in a range between a first power voltage and a second power voltage; a latch circuit configured to latch the voltage levels of the first output node and the second output node; a first variable load configured to adjust, based on a reset signal, an amount of current provided by a first power voltage terminal at the first power voltage to the first output node; a second variable load configured to adjust, based on the reset signal, an amount of current provided by the first power voltage terminal to the second output node; and a reset circuit configured to drive the first output node to the second power voltage based on the reset signal.