Patents by Inventor Kyu-Hyoun Kim
Kyu-Hyoun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11811416Abstract: An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform a successive approximation analog-to-digital conversion of an analog input, representing a result of multiplication of first and second vectors, to a digital output by determining an upper bound on the result of multiplication of the first and second vectors, identifying, based at least in part on the determined upper bound, at least a portion of the successive approximation analog-to-digital conversion to be skipped, and skipping the identified portion of the successive approximation analog-to-digital conversion.Type: GrantFiled: December 14, 2021Date of Patent: November 7, 2023Assignee: International Business Machines CorporationInventors: Kyu-hyoun Kim, Mingu Kang, Ankur Agrawal, Monodeep Kar
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Patent number: 11698842Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.Type: GrantFiled: October 7, 2021Date of Patent: July 11, 2023Assignee: International Business Machines CorporationInventors: Stephen Glancy, Kyu-hyoun Kim, Warren E. Maule, Kevin M. Mcilvain
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Patent number: 11687468Abstract: A memory system for storing data that includes providing a memory module having one or more memory devices and a voltage regulator for controlling voltage levels supplied to the one or more memory devices, wherein the voltage regulator has a first state that permits write and read operations with the one or more memory devices, and a second state where the voltage regulator prevents at least read operations with the one or more memory devices the system configured to store an encryption key in ROM on the voltage regulator; copy the encryption key value from the ROM to a voltage regulator register; set a voltage regulator encryption timer for a period of time; and transition the voltage regulator to the second state in response to the voltage regulator encryption timer expiring.Type: GrantFiled: July 2, 2020Date of Patent: June 27, 2023Assignee: International Business Machines CorporationInventors: Brian J. Connolly, Kyu-hyoun Kim
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Publication number: 20230188146Abstract: An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform a successive approximation analog-to-digital conversion of an analog input, representing a result of multiplication of first and second vectors, to a digital output by determining an upper bound on the result of multiplication of the first and second vectors, identifying, based at least in part on the determined upper bound, at least a portion of the successive approximation analog-to-digital conversion to be skipped, and skipping the identified portion of the successive approximation analog-to-digital conversion.Type: ApplicationFiled: December 14, 2021Publication date: June 15, 2023Inventors: Kyu-hyoun Kim, Mingu Kang, Ankur Agrawal, Monodeep Kar
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Patent number: 11645171Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.Type: GrantFiled: October 7, 2021Date of Patent: May 9, 2023Assignee: International Business Machines CorporationInventors: Stephen Glancy, Kyu-hyoun Kim, Warren E. Maule, Kevin M. Mcilvain
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Publication number: 20230083270Abstract: An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform, with a first accuracy, a first portion of a bitwise multiplication of first and second digital inputs and to perform, with a second accuracy different than the first accuracy, at least a second portion of the bitwise multiplication.Type: ApplicationFiled: September 14, 2021Publication date: March 16, 2023Inventors: Ankur Agrawal, Mingu Kang, Kyu-hyoun Kim, Monodeep Kar
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Patent number: 11593196Abstract: A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.Type: GrantFiled: December 1, 2021Date of Patent: February 28, 2023Assignee: International Business Machines CorporationInventors: Kevin M. Mcilvain, Warren E. Maule, Stephen Glancy, Kyu-hyoun Kim, Edgar R. Cordero
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Publication number: 20230058641Abstract: Techniques for performing analog-to-digital conversion are disclosed. For example, a method performs an analog-to-digital conversion of an analog input to a digital output comprising a set of bits, the set of bits comprising a most significant bit and one or more additional bits, the analog-to-digital conversion starting at a given one of the one or more additional bits following the most significant bit.Type: ApplicationFiled: August 19, 2021Publication date: February 23, 2023Inventors: Monodeep Kar, Ankur Agrawal, Mingu Kang, Kyu-hyoun Kim
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Patent number: 11562235Abstract: A computer-implemented method for improving the efficiency of computing an activation function in a neural network system includes initializing, by a controller, weights in a weight vector associated with the neural network system. Further, the method includes receiving, by the controller, an input vector of input values for computing a dot product with the weight vector for the activation function, which determines an output value of a node in the neural network system. The method further includes predicting, by a rectifier linear unit (ReLU), which computes the activation function, that the output value of the node will be negative based on computing an intermediate value for computing the dot product, and based on a magnitude of the intermediate value exceeding a precomputed threshold value. Further, the method includes, in response to the prediction, terminating, by the ReLU, the computation of the dot product, and outputting a 0 as the output value.Type: GrantFiled: February 21, 2020Date of Patent: January 24, 2023Assignee: International Business Machines CorporationInventors: Mingu Kang, Kyu-Hyoun Kim, Seyoung Kim, Chia-Yu Chen
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Publication number: 20220318603Abstract: A system, method, and computer program product for a neural network inference engine is disclosed. The inference engine system may include a first memory and a processor in communication with the first memory. The processor may be configured to perform operations. The operations the processor is configured to perform may include fetching a first task with said first memory and delivering the first task to the processor for processing the first task. The operations may further include prefetching a second task with the first memory while the processor is processing the first task. The operations may further include the first memory delivering the second task to the processor upon completion of processing the first task. The operations may further include the processor processing the second task.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Inventors: Arvind Kumar, Kyu-hyoun Kim, Ramachandra Divakaruni, Jeffrey Lyn Burns
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Patent number: 11342697Abstract: A card, e.g. a printed circuit board (PCB), has one or more conductive layers and one or more non-conductive layers disposed and alternating upon one another to form a stack. One or more of the conductive layers has one or more wiring elements within the conductive layer. The PCB/card has one or more card edges. The PCB also has a plurality of dual-level pad structures on each of one or more of the card edges. The dual-level pad structures each have an upper level, a lower level, and two or more walls. The lower level is a conductive pad with conductive surface. At least one of the conductive pads electrically connects to one or more of the wiring elements and/or one or more vias. In each of the dual-level pad structures, the walls and upper level may be made of an electrically non-conductive, insulating, or dielectric material or may be covered with a conductive material that electrically connects to conductive surface.Type: GrantFiled: June 4, 2020Date of Patent: May 24, 2022Assignee: International Business Machines CorporationInventors: Paul W Coteus, Thomas Cipolla, Kyu-hyoun Kim, Edmund Blackshear
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Patent number: 11314483Abstract: A system is provided for error resiliency in a bit serial computation. A delay monitor enforces an overall processing duration threshold for bit-serial processing all iterations for the bit serial computation, while determining a threshold for processing each iteration. At least some iterations correspond to a respective bit in an input bit sequence. A clock generator generates a clock signal for controlling a performance of the iterations. Each of iteration units perform a particular iteration, starting with a Most Significant Bit (MSB) of the input bit sequence and continuing in descending bit significant order, and by selectively increasing the threshold for at least one iteration while skipping from processing at least one subsequent iteration whose iteration-level processing duration exceeds a remaining amount of an overall processing duration for all iterations, responsive to the at least one iteration requiring more time to complete than a current value of the threshold.Type: GrantFiled: January 8, 2020Date of Patent: April 26, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mingu Kang, Seyoung Kim, Kyu-hyoun Kim, Eun Kyung Lee
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Patent number: 11301211Abstract: A differential mixed-signal logic processor is provided. The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B. Each of the plurality of mixed-signal multiplier branches include a first capacitor connected across a second capacitor and a third capacitor to provide a differential output across the second and third capacitors. A capacitance of the first capacitor is equal to half a capacitance of the second and third capacitors.Type: GrantFiled: April 13, 2020Date of Patent: April 12, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Seyoung Kim, Mingu Kang, Kyu-hyoun Kim, Seonghoon Woo
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Publication number: 20220091927Abstract: A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.Type: ApplicationFiled: December 1, 2021Publication date: March 24, 2022Inventors: Kevin M. Mcilvain, Warren E. Maule, Stephen Glancy, Kyu-hyoun Kim, Edgar R. Cordero
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Patent number: 11264077Abstract: A memory subsystem is disclosed comprising at least one memory module, the memory module having a substrate to which a plurality of memory chips is mounted and a voltage regulator, the voltage regulator receiving a power supply signal from a system power supply and outputting two or more power signals, each power signal providing a different, regulated voltage, which regulated voltages are each routed to each of the memory chips; and a redundant voltage regulator external to and not mounted on the memory module and configured to output two or more power signals, providing external different, regulated voltages which are the same voltages as the voltages output by the voltage regulator on the memory module, and supplying the two or more signals to the memory module.Type: GrantFiled: January 15, 2021Date of Patent: March 1, 2022Assignee: International Business Machines CorporationInventors: Brian J. Connolly, Kyu-Hyoun Kim, Warren E. Maule
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Publication number: 20220027243Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.Type: ApplicationFiled: October 7, 2021Publication date: January 27, 2022Inventors: Stephen Glancy, Kyu-hyoun Kim, Warren E. Maule, Kevin M. Mcilvain
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Publication number: 20220004506Abstract: A memory system for storing data that includes providing a memory module having one or more memory devices and a voltage regulator for controlling voltage levels supplied to the one or more memory devices, wherein the voltage regulator has a first state that permits write and read operations with the one or more memory devices, and a second state where the voltage regulator prevents at least read operations with the one or more memory devices the system configured to store an encryption key in ROM on the voltage regulator; copy the encryption key value from the ROM to a voltage regulator register; set a voltage regulator encryption timer for a period of time; and transition the voltage regulator to the second state in response to the voltage regulator encryption timer expiring.Type: ApplicationFiled: July 2, 2020Publication date: January 6, 2022Inventors: Brian J. Connolly, Kyu-hyoun Kim
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Patent number: 11200112Abstract: A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.Type: GrantFiled: August 24, 2020Date of Patent: December 14, 2021Assignee: International Business Machines CorporationInventors: Kevin M. Mcilvain, Warren E. Maule, Stephen Glancy, Kyu-hyoun Kim, Edgar R. Cordero
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Publication number: 20210384661Abstract: A card, e.g. a printed circuit board (PCB), has one or more conductive layers and one or more non-conductive layers disposed and alternating upon one another to form a stack. One or more of the conductive layers has one or more wiring elements within the conductive layer. The PCB/card has one or more card edges. The PCB also has a plurality of dual-level pad structures on each of one or more of the card edges. The dual-level pad structures each have an upper level, a lower level, and two or more walls. The lower level is a conductive pad with conductive surface. At least one of the conductive pads electrically connects to one or more of the wiring elements and/or one or more vias. In each of the dual-level pad structures, the walls and upper level may be made of an electrically non-conductive, insulating, or dielectric material or may be covered with a conductive material that electrically connects to conductive surface.Type: ApplicationFiled: June 4, 2020Publication date: December 9, 2021Inventors: Paul W. Coteus, Thomas Cipolla, Kyu-hyoun Kim, Edmund Blackshear
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Patent number: 11182262Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.Type: GrantFiled: March 24, 2020Date of Patent: November 23, 2021Assignee: International Business Machines CorporationInventors: Stephen Glancy, Kyu-hyoun Kim, Warren E. Maule, Kevin M. Mcilvain