Patents by Inventor Kyu-Hyoun Kim

Kyu-Hyoun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12261619
    Abstract: An apparatus includes multiple analog to digital converters. Individual analog to digital converters are configured to produce a digital output from an analog input and configured to compute a least significant bit of the digital output by comparing an internal residual voltage for determination of the least significant bit and a residual voltage from another analog to digital converter.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: March 25, 2025
    Assignee: International Business Machines Corporation
    Inventors: Chia-Yu Chen, Ankur Agrawal, Andrea Fasoli, Kyu-hyoun Kim
  • Publication number: 20250077804
    Abstract: A first circuit is configured to split a first integer value into a first coarse value and a first fine value, and split a second integer value into a second coarse value and a second fine value. A second circuit performs an analog multiply and accumulate (MAC) operation on the first and second coarse values to produce a first analog output, perform an analog MAC operation on the first coarse value and the second fine value to produce a second analog output, perform an analog MAC operation on the first fine value and the second coarse value to produce a third analog output, and perform an analog MAC operation on the first and second fine values together to produce a fourth analog output. A third circuit is configured to perform analog-to-digital (A/D) conversion on and combine the analog output signals to produce a reconstructed digital output signal.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 6, 2025
    Inventors: Ankur Agrawal, Andrea Fasoli, Monodeep Kar, Kyu-hyoun Kim, Sergey Rylov, Chia-Yu Chen, Xiao Sun
  • Patent number: 12118329
    Abstract: Mixed signal multipliers and methods for operating the same include a sampling capacitor and an accumulate capacitor. A sampling switch is configured to store an analog value on the sampling capacitor when a digital bit value of a digital signal is one and to store a zero when the digital bit value of the digital signal is a zero. An accumulate switch is configured to store an average of the stored value of the sampling capacitor and a previous stored value of the accumulate capacitor. A processor is configured to alternately trigger the sampling capacitor and the sampling capacitor for each bit value in the digital signal.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: October 15, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mingu Kang, Seyoung Kim, Kyu-Hyoun Kim
  • Publication number: 20240250070
    Abstract: Embodiments of the present invention are directed to processing methods and resulting structures for three-dimensional integrated circuits (3D ICs) having facilitator dies in a hierarchical configuration. In a non-limiting embodiment, a method includes forming a plurality of stacked dies. The plurality of stacked dies includes a bottom die having a first die type, a plurality of upper dies having a second die type different than the first die type, and a facilitator die having a third die type different than the first die type and the second die type. At least one of a signal connection and a power distribution line are formed hierarchically between the bottom die, the plurality of upper dies, and the facilitator die.
    Type: Application
    Filed: January 25, 2023
    Publication date: July 25, 2024
    Inventors: Kyu-hyoun Kim, Arvind Kumar, Joshua M. Rubin, John W. Golz, Mounir Meghelli
  • Publication number: 20240204792
    Abstract: An apparatus includes multiple analog to digital converters. Individual analog to digital converters are configured to produce a digital output from an analog input and configured to compute a least significant bit of the digital output by comparing an internal residual voltage for determination of the least significant bit and a residual voltage from another analog to digital converter.
    Type: Application
    Filed: December 20, 2022
    Publication date: June 20, 2024
    Inventors: Chia-Yu CHEN, Ankur Agrawal, Andrea Fasoli, Kyu-hyoun Kim
  • Publication number: 20240176584
    Abstract: An apparatus comprising: a first plurality of inputs representing an activation input vector; a second plurality of inputs representing a weight input vector; an analog multiplier-and-accumulator to generate a first analog voltage representing a first multiply-and-accumulate result for the said first inputs and the second inputs; a voltage multiplier that takes the said first analog voltage and produces a second analog voltage representing, a second multiply-and-accumulate result by multiplying at least one scaling factor to the first analog voltage; an analog to digital converter configured to convert the said second analog voltage multiply-and-accumulate result into a digital signal using a limited-precision operation during a neural network inference operation; and a hardware controller configured to determine the at least one scaling factor based on the first multiply-and-accumulate result, or a software controller configured to determine the at least one scaling factor based on the first multiply-and-acc
    Type: Application
    Filed: November 29, 2022
    Publication date: May 30, 2024
    Inventors: Chia-Yu Chen, Andrea Fasoli, Ankur Agrawal, Kyu-hyoun Kim, Chi-Chun LIU, Mauricio J. Serrano, Monodeep Kar, Naigang Wang, Leland Chang
  • Patent number: 11811416
    Abstract: An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform a successive approximation analog-to-digital conversion of an analog input, representing a result of multiplication of first and second vectors, to a digital output by determining an upper bound on the result of multiplication of the first and second vectors, identifying, based at least in part on the determined upper bound, at least a portion of the successive approximation analog-to-digital conversion to be skipped, and skipping the identified portion of the successive approximation analog-to-digital conversion.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: November 7, 2023
    Assignee: International Business Machines Corporation
    Inventors: Kyu-hyoun Kim, Mingu Kang, Ankur Agrawal, Monodeep Kar
  • Patent number: 11698842
    Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: July 11, 2023
    Assignee: International Business Machines Corporation
    Inventors: Stephen Glancy, Kyu-hyoun Kim, Warren E. Maule, Kevin M. Mcilvain
  • Patent number: 11687468
    Abstract: A memory system for storing data that includes providing a memory module having one or more memory devices and a voltage regulator for controlling voltage levels supplied to the one or more memory devices, wherein the voltage regulator has a first state that permits write and read operations with the one or more memory devices, and a second state where the voltage regulator prevents at least read operations with the one or more memory devices the system configured to store an encryption key in ROM on the voltage regulator; copy the encryption key value from the ROM to a voltage regulator register; set a voltage regulator encryption timer for a period of time; and transition the voltage regulator to the second state in response to the voltage regulator encryption timer expiring.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: June 27, 2023
    Assignee: International Business Machines Corporation
    Inventors: Brian J. Connolly, Kyu-hyoun Kim
  • Publication number: 20230188146
    Abstract: An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform a successive approximation analog-to-digital conversion of an analog input, representing a result of multiplication of first and second vectors, to a digital output by determining an upper bound on the result of multiplication of the first and second vectors, identifying, based at least in part on the determined upper bound, at least a portion of the successive approximation analog-to-digital conversion to be skipped, and skipping the identified portion of the successive approximation analog-to-digital conversion.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 15, 2023
    Inventors: Kyu-hyoun Kim, Mingu Kang, Ankur Agrawal, Monodeep Kar
  • Patent number: 11645171
    Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: May 9, 2023
    Assignee: International Business Machines Corporation
    Inventors: Stephen Glancy, Kyu-hyoun Kim, Warren E. Maule, Kevin M. Mcilvain
  • Publication number: 20230083270
    Abstract: An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform, with a first accuracy, a first portion of a bitwise multiplication of first and second digital inputs and to perform, with a second accuracy different than the first accuracy, at least a second portion of the bitwise multiplication.
    Type: Application
    Filed: September 14, 2021
    Publication date: March 16, 2023
    Inventors: Ankur Agrawal, Mingu Kang, Kyu-hyoun Kim, Monodeep Kar
  • Patent number: 11593196
    Abstract: A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: February 28, 2023
    Assignee: International Business Machines Corporation
    Inventors: Kevin M. Mcilvain, Warren E. Maule, Stephen Glancy, Kyu-hyoun Kim, Edgar R. Cordero
  • Publication number: 20230058641
    Abstract: Techniques for performing analog-to-digital conversion are disclosed. For example, a method performs an analog-to-digital conversion of an analog input to a digital output comprising a set of bits, the set of bits comprising a most significant bit and one or more additional bits, the analog-to-digital conversion starting at a given one of the one or more additional bits following the most significant bit.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Inventors: Monodeep Kar, Ankur Agrawal, Mingu Kang, Kyu-hyoun Kim
  • Patent number: 11562235
    Abstract: A computer-implemented method for improving the efficiency of computing an activation function in a neural network system includes initializing, by a controller, weights in a weight vector associated with the neural network system. Further, the method includes receiving, by the controller, an input vector of input values for computing a dot product with the weight vector for the activation function, which determines an output value of a node in the neural network system. The method further includes predicting, by a rectifier linear unit (ReLU), which computes the activation function, that the output value of the node will be negative based on computing an intermediate value for computing the dot product, and based on a magnitude of the intermediate value exceeding a precomputed threshold value. Further, the method includes, in response to the prediction, terminating, by the ReLU, the computation of the dot product, and outputting a 0 as the output value.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: January 24, 2023
    Assignee: International Business Machines Corporation
    Inventors: Mingu Kang, Kyu-Hyoun Kim, Seyoung Kim, Chia-Yu Chen
  • Publication number: 20220318603
    Abstract: A system, method, and computer program product for a neural network inference engine is disclosed. The inference engine system may include a first memory and a processor in communication with the first memory. The processor may be configured to perform operations. The operations the processor is configured to perform may include fetching a first task with said first memory and delivering the first task to the processor for processing the first task. The operations may further include prefetching a second task with the first memory while the processor is processing the first task. The operations may further include the first memory delivering the second task to the processor upon completion of processing the first task. The operations may further include the processor processing the second task.
    Type: Application
    Filed: March 31, 2021
    Publication date: October 6, 2022
    Inventors: Arvind Kumar, Kyu-hyoun Kim, Ramachandra Divakaruni, Jeffrey Lyn Burns
  • Patent number: 11342697
    Abstract: A card, e.g. a printed circuit board (PCB), has one or more conductive layers and one or more non-conductive layers disposed and alternating upon one another to form a stack. One or more of the conductive layers has one or more wiring elements within the conductive layer. The PCB/card has one or more card edges. The PCB also has a plurality of dual-level pad structures on each of one or more of the card edges. The dual-level pad structures each have an upper level, a lower level, and two or more walls. The lower level is a conductive pad with conductive surface. At least one of the conductive pads electrically connects to one or more of the wiring elements and/or one or more vias. In each of the dual-level pad structures, the walls and upper level may be made of an electrically non-conductive, insulating, or dielectric material or may be covered with a conductive material that electrically connects to conductive surface.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: May 24, 2022
    Assignee: International Business Machines Corporation
    Inventors: Paul W Coteus, Thomas Cipolla, Kyu-hyoun Kim, Edmund Blackshear
  • Patent number: 11314483
    Abstract: A system is provided for error resiliency in a bit serial computation. A delay monitor enforces an overall processing duration threshold for bit-serial processing all iterations for the bit serial computation, while determining a threshold for processing each iteration. At least some iterations correspond to a respective bit in an input bit sequence. A clock generator generates a clock signal for controlling a performance of the iterations. Each of iteration units perform a particular iteration, starting with a Most Significant Bit (MSB) of the input bit sequence and continuing in descending bit significant order, and by selectively increasing the threshold for at least one iteration while skipping from processing at least one subsequent iteration whose iteration-level processing duration exceeds a remaining amount of an overall processing duration for all iterations, responsive to the at least one iteration requiring more time to complete than a current value of the threshold.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: April 26, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mingu Kang, Seyoung Kim, Kyu-hyoun Kim, Eun Kyung Lee
  • Patent number: 11301211
    Abstract: A differential mixed-signal logic processor is provided. The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B. Each of the plurality of mixed-signal multiplier branches include a first capacitor connected across a second capacitor and a third capacitor to provide a differential output across the second and third capacitors. A capacitance of the first capacitor is equal to half a capacitance of the second and third capacitors.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: April 12, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Seyoung Kim, Mingu Kang, Kyu-hyoun Kim, Seonghoon Woo
  • Publication number: 20220091927
    Abstract: A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.
    Type: Application
    Filed: December 1, 2021
    Publication date: March 24, 2022
    Inventors: Kevin M. Mcilvain, Warren E. Maule, Stephen Glancy, Kyu-hyoun Kim, Edgar R. Cordero